Automatic control systems (5th ed.)
Automatic control systems (5th ed.)
High-speed signal propagation on lossy transmission lines
IBM Journal of Research and Development
Delay evaluation with lumped linear RLC interconnect circuit models
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
RICE: Rapid interconnect circuit evaluator
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
RC interconnect optimization under the Elmore delay model
DAC '94 Proceedings of the 31st annual Design Automation Conference
Bounded-skew clock and Steiner routing under Elmore delay
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Coping with RC(L) interconnect design headaches
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Optimal wiresizing for interconnects with multiple sources
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Modeling and characterization of long on-chip interconnections for high-performance microprocessors
IBM Journal of Research and Development
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Optimal wiresizing under the distributed Elmore delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
Figures of merit to characterize the importance of on-chip inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Signal delay in RC tree networks
DAC '81 Proceedings of the 18th Design Automation Conference
Repeater insertion in tree structured inductive interconnect
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Reduced Order Modeling for RLC Interconnect Tree Using Hurwitz Polynomial
Analog Integrated Circuits and Signal Processing
Hurwitz stable reduced order modeling for RLC interconnect trees
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Analysis of Pulse Signaling for Low-Power On-Chip Global Bus Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
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