Analytical delay models for VLSI interconnects under ramp input
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Equivalent Elmore delay for RLC trees
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy efficiency bounds of pulse-encoded buses
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Semi-serial on-chip link implementation for energy efficiency and high throughput
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Pulse signaling is proposed for on-chip global bus design to reduce dynamic power consumption. To maximize power saving, shorter pulse width and longer propagation length are preferred. In this work, a complete set of analytical models are developed for pulse propagation along RLC lines. These models connect line geometries and electrical properties of an input pulse with several important design metrics, such as delay, pulse width, maximum propagation length, and power saving. Excellent model accuracy is achieved as compared to SPICE simulations. These models can be easily implemented into design tools to facilitate the optimization of pulse signaling on lossy on-chip global buses. Furthermore, pulse signaling can be integrated with a time-division scheme to further reduce power consumption. Using the newly developed models, it is demonstrated that more than 70% dynamic power can be saved in this scheme in on-chip bus design.