Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Journal of Parallel and Distributed Computing - Special issue on parallel computing with optical interconnects
Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Exploiting the on-chip inductance in high-speed clock distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices
High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices
RF and Microwave Circuit and Component Design for Wireless Systems
RF and Microwave Circuit and Component Design for Wireless Systems
Asynchronous Pulse Logic
Optimization of Wafer Scale H-Tree Clock Distribution Network Based on a New Statistical Skew Model
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Timing Characterization of Dual-Edge Triggered Flip-Flops
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Buffer insertion for noise and delay optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis of Pulse Signaling for Low-Power On-Chip Global Bus Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Energy efficiency bounds of pulse-encoded buses
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Improved ber performance in intra-chip rf/wireless interconnect systems
Proceedings of the 18th ACM Great Lakes symposium on VLSI
EMBRACE: emulating biologically-inspired architectures on hardware
NN'08 Proceedings of the 9th WSEAS International Conference on Neural Networks
Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Temperature-Aware Delay Borrowing for Energy-Efficient Low-Voltage Link Design
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A high-speed sample-and-hold circuit based on CMOS transmission lines
Analog Integrated Circuits and Signal Processing
Semi-serial on-chip link implementation for energy efficiency and high throughput
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Short pulse generation with on-chip pulse-forming lines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of a novel differential on-chip wave-pipelined serial interconnect with surfing
Microprocessors & Microsystems
METEOR: Hybrid photonic ring-mesh network-on-chip for multicore architectures
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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Pulsed wave interconnect is proposed for global interconnect applications. Signals are represented by localized wavepackets that propagate along the interconnect lines at the local speed of light to trigger the receivers. Energy consumption is reduced through charging up only part of the interconnect lines and using the voltage doubling property of the receiver gate capacitances. In a 0.18-µm CMOS technology case study, SPICE simulations show that pulsed wave interconnect can save up to 50% of energy and ∼30% of chip area in comparison with the repeater insertion method. A proposed signal splitting structure provides reasonable isolations between different receivers. Measured S-parameters of 3.8-mm interconnect lines fabricated through CMOS foundry showed that the distortion and attenuation of a pico second signal are much less serious than the theoretical predictions. Pulsed wave interconnect also enables time division application of a single line to boost its bit rate capacity. The use of nonlinear transmission lines (NLTL) is also proposed to overcome pulse broadening and attenuation caused by dispersion and frequency-dependent losses. Pulsed waves on an NLTL may be generated, transmitted, split and detected with components realizable in bulk and SOI CMOS technologies. Tapered NLTL can be used for pulse compression. NLTL edge sharpening abilities may be applicable for signal rise time control.