Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interconnect synthesis without wire tapering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In the literature, surfing technique has been proposed for single ended wave-pipelined serial interconnects to increase the data transfer rate. This uses uniform repeaters (UR). In this paper, two novel surfing techniques, one using uniform repeaters (UR) and another using non-uniform repeaters (NUR) are proposed for differential wave-pipelined serial interconnects. The method of logical effort is also proposed for the design of both UR and NUR. To evaluate the efficiency of these techniques, 40mm metal 4 interconnects using the proposed surfing techniques are implemented along with transmitter, receiver and delay locked loop(DLL) in UMC 180nm technology and their performances are studied through post layout simulations. From this study, it is observed that the differential surfing technique using UR and NUR achieve 3.0 times and 4.15 times higher data rates respectively compared to the single ended scheme whose maximum data rate is 1.33GB/s.