Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploiting the on-chip inductance in high-speed clock distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
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Hurwitz stable reduced order modeling for RLC interconnect trees
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Shielding effect of on-chip interconnect inductance
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On-Chip Communication Architectures: System on Chip Interconnect
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Integration, the VLSI Journal
Timing optimization in logic with interconnect
Proceedings of the 2008 international workshop on System level interconnect prediction
Parallel vs. serial on-chip communication
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3-D topologies for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Three-dimensional Integrated Circuit Design
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On-chip optical interconnect for reduced delay uncertainty
Proceedings of the 2nd international conference on Nano-Networks
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Reducing interconnect delay uncertainty via hybrid polarity repeater insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Simultaneous shield and repeater insertion
Proceedings of the 19th ACM Great Lakes symposium on VLSI
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NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A methodology for the characterization of process variation in NoC links
Proceedings of the Conference on Design, Automation and Test in Europe
Resource based optimization for simultaneous shield and repeater insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools
Microelectronics Journal
Variability aware low-power delay optimal buffer insertion for global interconnects
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE system-on-chip conference
Characterizing the impact of process variation on 45 nm NoC-based CMPs
Journal of Parallel and Distributed Computing
Repeater insertion in power-managed VLSI systems
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Variability-tolerant NoC link design
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Microprocessors & Microsystems
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Interconnect plays an increasingly important role in deep-submicrometer very large scale integrated technologies. Multiple design criteria are considered in interconnect design, such as delay, power, and bandwidth. In this paper, a repeater insertion methodology is presented for achieving the minimum power in an RC interconnect while satisfying delay and bandwidth constraints. These constraints determine a design space for the number and size of the repeaters. The minimum power is shown to occur at the edge of the design space. With delay constraints, closed form solutions for the minimum power are developed, where the average error is 7% as compared with SPICE. With bandwidth constraints, the minimum power can be achieved with minimum-sized repeaters. The effects of inductance on the delay, bandwidth, and power of an RLC interconnect with repeaters are also analyzed. By including inductance, the minimum interconnect power under a delay or bandwidth constraint decreases as compared with an RC interconnect.