DAC '98 Proceedings of the 35th annual Design Automation Conference
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Interconnect-aware high-level synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Practical repeater insertion for low power: what repeater library do we need?
Proceedings of the 41st annual Design Automation Conference
A High-level Interconnect Power Model for Design Space Exploration
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
DVS for On-Chip Bus Designs Based on Timing Error Correction
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
An efficient technology mapping algorithm targeting routing congestion under delay constraints
Proceedings of the 2005 international symposium on Physical design
A sensitivity analysis of low-power repeater insertion
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Proceedings of the 42nd annual Design Automation Conference
Replacing global wires with an on-chip network: a power analysis
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A power aware system level interconnect design methodology for latency-insensitive systems
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power repeater insertion with both delay and slew rate constraints
Proceedings of the 43rd annual Design Automation Conference
Elmore model for energy estimation in RC trees
Proceedings of the 43rd annual Design Automation Conference
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
ReCycle:: pipeline adaptation to tolerate process variation
Proceedings of the 34th annual international symposium on Computer architecture
Thermal-aware methodology for repeater insertion in low-power VLSI circuits
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Thermal-aware task scheduling at the system software level
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Energy optimization of multiprocessor systems on chip by voltage selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thermal-aware methodology for repeater insertion in low-power VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power and high-performance techniques in global interconnect signaling
Microelectronics Journal
Performance prediction of throughput-centric pipelined global interconnects with voltage scaling
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
A power-efficient multipin ILP-based routing technique
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Physical vs. Virtual Express Topologies with Low-Swing Links for Future Many-Core NoCs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Dynamic thermal management in 3D multicore architectures
Proceedings of the Conference on Design, Automation and Test in Europe
A high sensitivity and process tolerant digital thermal sensing scheme for 3-D Ics
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
On-chip interconnect analysis of performance and energy metrics under different design goals
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The purpose of this work is two fold. First, to quantify and establish future trends for the dynamic power dissipation in global wires of high performance integrated circuits. Second, to develop a novel and efficient delay-power tradeoff formulation for minimizing power due to repeaters, which can otherwise constitute 50% of total global wire power dissipation. Using the closed form solutions from this formulation, power savings of 50% on repeaters are shown with minimal delay penalties of about 5% at the 50 nm technology node. These closed-form, analytical solutions provide a fast and powerful tool for designers to minimize power.