Express Cubes: Improving the Performance of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Proceedings of the 39th annual Design Automation Conference
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Express virtual channels: towards the ideal interconnection fabric
Proceedings of the 34th annual international symposium on Computer architecture
Flattened Butterfly Topology for On-Chip Networks
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
Concurrent hybrid switching for massively parallel systems-on-chip: the CYBER architecture
Proceedings of the 9th conference on Computing Frontiers
Self-aware computing in the Angstrom processor
Proceedings of the 49th Annual Design Automation Conference
Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI
Proceedings of the 49th Annual Design Automation Conference
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The number of cores present on-chip is increasing rapidly. The on-chip network that connects these cores needs to scale efficiently. The topology of on-chip networks is an important design choice that affects how these networks scale. Most current on-chip networks use 2-D mesh topologies which do not scale due to their large diameter and energy inefficiency. To tackle the scalability problem of 2-D meshes, various physical express topologies and virtual express topologies have been proposed. In addition, recently proposed link designs like capacitively driven low-swing interconnects can help lower link power and latency, and can favor these bypass designs. In this work, we compare these two kinds of express topologies under realistic system constraints using synthetic network traffic. We observe that both express topologies help reduce low-load latencies. Virtual topologies help improve throughput whereas the physical express topologies give better performance-per-watt.