Token flow control

Authors:
Amit Kumar;Li-Shiuan Peh;Niraj K. Jha
Affiliations:
Department of Electrical Engineering, Princeton University, NJ 08544, USA;Department of Electrical Engineering, Princeton University, NJ 08544, USA;Department of Electrical Engineering, Princeton University, NJ 08544, USA
Venue:
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Year:
2008

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Abstract

As companies move towards many-core chips, an efficient on-chip communication fabric to connect these cores assumes critical importance. To address limitations to wire delay scalability and increasing bandwidth demands, state-of-the-art on-chip networks use a modular packet-switched design with routers at every hop which allow sharing of network channels over multiple packet flows. This, however, leads to packets going through a complex router pipeline at every hop, resulting in the overall communication energy/delay being dominated by the router overhead, as opposed to just wire energy/delay.