Performance Analysis of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
Express Cubes: Improving the Performance of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Segmented bus design for low-power systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Piranha: a scalable architecture based on single-chip multiprocessing
Proceedings of the 27th annual international symposium on Computer architecture
Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Powering networks on chips: energy-efficient and reliable interconnect design for SoCs
Proceedings of the 14th international symposium on Systems synthesis
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
PowerHerd: dynamic satisfaction of peak power constraints in interconnection networks
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architectures
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Power constrained design of multiprocessor interconnection networks
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
Proceedings of the 30th annual international symposium on Computer architecture
Leakage power modeling and optimization in interconnection networks
Proceedings of the 2003 international symposium on Low power electronics and design
Energy characterization of a tiled architecture processor with on-chip networks
Proceedings of the 2003 international symposium on Low power electronics and design
Blue Gene: a vision for protein science using a petaflop supercomputer
IBM Systems Journal - Deep computing for the life sciences
POWER4 system microarchitecture
IBM Journal of Research and Development
FIFO power optimization for on-chip networks
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Power-aware communication optimization for networks-on-chips with voltage scalable links
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Thermal Modeling, Characterization and Management of On-Chip Networks
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
On-Chip Interconnects and Instruction Steering Schemes for Clustered Microarchitectures
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A low latency router supporting adaptivity for on-chip interconnects
Proceedings of the 42nd annual Design Automation Conference
Microarchitecture of a High-Radix Router
Proceedings of the 32nd annual international symposium on Computer Architecture
Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks
Proceedings of the 32nd annual international symposium on Computer Architecture
Compiler-directed proactive power management for networks
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
A Distributed Control Path Architecture for VLIW Processors
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
Analysis of Error Recovery Schemes for Networks on Chips
IEEE Design & Test
Power reduction techniques for microprocessor systems
ACM Computing Surveys (CSUR)
Using data replication to reduce communication energy on chip multiprocessors
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
NoCEE: energy macro-model extraction methodology for network on chip routers
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
Proceedings of the 33rd annual international symposium on Computer Architecture
Design tradeoffs for tiled CMP on-chip networks
Proceedings of the 20th annual international conference on Supercomputing
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Flattened butterfly: a cost-efficient topology for high-radix networks
Proceedings of the 34th annual international symposium on Computer architecture
Express virtual channels: towards the ideal interconnection fabric
Proceedings of the 34th annual international symposium on Computer architecture
SAPP: scalable and adaptable peak power management in nocs
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems
Trends toward on-chip networked microsystems
International Journal of High Performance Computing and Networking
Software-directed combined cpu/link voltage scaling fornoc-based cmps
SIGMETRICS '08 Proceedings of the 2008 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
3-D topologies for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Impact of Process and Temperature Variations on Network-on-Chip Design Exploration
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Statistical Approach to NoC Design
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
The Journal of Supercomputing
Zero-efficient buffer design for reliable network-on-chip in tiled chip-multi-processor
Proceedings of the conference on Design, automation and test in Europe
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Integration, the VLSI Journal
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Frequent value compression in packet-based NoC architectures
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Reliability aware NoC router architecture using input channel buffer sharing
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Polaris: a system-level roadmapping toolchain for on-chip interconnection networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic packet fragmentation for increased virtual channel utilization in on-chip routers
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Custom networks-on-chip architectures with multicast routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Segment gating for static energy reduction in Networks-on-Chip
Proceedings of the 2nd International Workshop on Network on Chip Architectures
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SCARAB: a single cycle adaptive routing and bufferless network
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Low-cost router microarchitecture for on-chip networks
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
An analysis of on-chip interconnection networks for large-scale chip multiprocessors
ACM Transactions on Architecture and Code Optimization (TACO)
A scalable organization for distributed directories
Journal of Systems Architecture: the EUROMICRO Journal
HiPC'07 Proceedings of the 14th international conference on High performance computing
Communication-aware task assignment algorithm for MPSoC using shared memory
Journal of Systems Architecture: the EUROMICRO Journal
Evaluating Bufferless Flow Control for On-chip Networks
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Design of a High-Throughput Distributed Shared-Buffer NoC Router
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Temperature-Aware Delay Borrowing for Energy-Efficient Low-Voltage Link Design
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
An overview of achieving energy efficiency in on-chip networks
International Journal of Communication Networks and Distributed Systems
Light NUCA: a proposal for bridging the inter-cache latency gap
Proceedings of the Conference on Design, Automation and Test in Europe
Optimizing power and performance for reliable on-chip networks
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Adaptive Flow Control for Robust Performance and Energy
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Design of a performance enhanced and power reduced dual-crossbar Network-on-Chip (NoC) architecture
Microprocessors & Microsystems
Prevention flow-control for low latency torus Networks-on-Chip
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees
Proceedings of the 38th annual international symposium on Computer architecture
NoC frequency scaling with flexible-pipeline routers
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Evaluation of low-overhead organizations for the directory in future many-core CMPs
Euro-Par 2010 Proceedings of the 2010 conference on Parallel processing
Exploring energy-performance trade-offs for heterogeneous interconnect clustered VLIW processors
HiPC'06 Proceedings of the 13th international conference on High Performance Computing
Co-design of channel buffers and crossbar organizations in NoCs architectures
Proceedings of the International Conference on Computer-Aided Design
A low-swing crossbar and link generator for low-power networks-on-chip
Proceedings of the International Conference on Computer-Aided Design
Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
FLEXclusion: balancing cache capacity and on-chip bandwidth via flexible exclusion
Proceedings of the 39th Annual International Symposium on Computer Architecture
Optimal placement of frequently accessed IPs in mesh NoCs
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
Moths: Mobile threads for on-chip networks
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
NOC-Out: Microarchitecting a Scale-Out Processor
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Switch folding: network-on-chip routers with time-multiplexed output ports
Proceedings of the Conference on Design, Automation and Test in Europe
Exploring topologies for source-synchronous ring-based network-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Catnap: energy proportional multiple network-on-chip
Proceedings of the 40th Annual International Symposium on Computer Architecture
Dynamic voltage and frequency scaling for shared resources in multicore processor designs
Proceedings of the 50th Annual Design Automation Conference
Randomized partially-minimal routing: near-optimal oblivious routing for 3-D mesh networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic directories: a mechanism for reducing on-chip interconnect power in multicores
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A fast, source-synchronous ring-based network-on-chip design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Silicon-aware distributed switch architecture for on-chip networks
Journal of Systems Architecture: the EUROMICRO Journal
| Hi-index | 0.00 |
As demand for bandwidth increases in systems-on-a-chipand chip multiprocessors, networks are fast replacing busesand dedicated wires as the pervasive interconnect fabric foron-chip communication. The tight delay requirements facedby on-chip networks have resulted in prior microarchitecturesbeing largely performance-driven. While performanceis a critical metric, on-chip networks are also extremelypower-constrained. In this paper, we investigate on-chipnetwork microarchitectures from a power-driven perspective.We first analyze the power dissipation of existing networkmicroarchitectures, highlighting insights that promptus to devise several power-efficient network microarchitectures:segmented crossbar, cut-through crossbar and write-throughbuffer. We also study and uncover the power savingpotential of an existing network architecture: expresscube. These techniques are evaluated with synthetic as wellas real chip multiprocessor traces, showing a reduction innetwork power of up to 44.9%, along with no degradationin network performance, and even improved latency-throughputin some cases.