Zero-efficient buffer design for reliable network-on-chip in tiled chip-multi-processor

Authors:
Jun Wang;Hongbo Zeng;Kun Huang;Ge Zhang;Yan Tang
Affiliations:
Institute of Computing Technology, Chinese Academy of Sciences;Institute of Computing Technology, Chinese Academy of Sciences;Institute of Computing Technology, Chinese Academy of Sciences;Institute of Computing Technology, Chinese Academy of Sciences;The Ohio State University
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2008

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Abstract

Network-on-Chip (NoC) is a promising solution for efficient interconnection between processor cores in Chip-Multi-Processor (CMP). This paper is focusing on the energy-efficient design of buffers, a group of the most important components in NoC. From our investigation, an overwhelming majority of "zero" is contained in the packets transmitting in NoC for CMP. A zero-efficient buffer design is proposed as well as the error control scheme. Compared with conventional design, up to 43% energy consumption can be saved. We use a 90nm CMOS process in our simulation.