Microarchitecture of the Godson-2 processor

Authors:
Wei-Wu Hu;Fu-Xin Zhang;Zu-Song Li
Affiliations:
Institute of Computing Technology, Chinese Academy of Sciences, Beijing, P.R. China;Institute of Computing Technology, Chinese Academy of Sciences, Beijing, P.R. China;Institute of Computing Technology, Chinese Academy of Sciences, Beijing, P.R. China
Venue:
Journal of Computer Science and Technology
Year:
2005

Citing 6
Cited 13

Computer architecture: a quantitative approach

Computer architecture: a quantitative approach
The MIPS R10000 Superscalar Microprocessor

IEEE Micro
The HP PA-8000 RISC CPU

IEEE Micro
The Alpha 21264 Microprocessor

IEEE Micro
UltraSPARC-III: Designing Third-Generation 64-Bit Performance

IEEE Micro
Introducing the IA-64 Architecture

IEEE Micro

Code reordering on limited branch offset

ACM Transactions on Architecture and Code Optimization (TACO)
Embedded test decompressor to reduce the required channels and vector memory of tester for complex processor circuit

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Zero-efficient buffer design for reliable network-on-chip in tiled chip-multi-processor

Proceedings of the conference on Design, automation and test in Europe
Making effective decisions in computer architects' real-world: lessons and experiences with Godson-2 processor designs

Journal of Computer Science and Technology
Implementing a 1GHz four-issue out-of-order execution microprocessor in a standard cell ASIC methodology

Journal of Computer Science and Technology
Characterizing and Understanding the Bandwidth Behavior of Workloads on Multi-core Processors

Euro-Par '09 Proceedings of the 15th International Euro-Par Conference on Parallel Processing
A multi-FPGA based platform for emulating a 100m-transistor-scale processor with high-speed peripherals (abstract only)

Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Optimized register renaming scheme for stack-based x86 operations

ARCS'07 Proceedings of the 20th international conference on Architecture of computing systems
Efficient binary translation system with low hardware cost

ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Chip multithreaded consistency model

Journal of Computer Science and Technology
Processor directed dynamic page policy

ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
A memory bandwidth effective cache store miss policy

ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Concerning with on-chip network features to improve cache coherence protocols for CMPs

ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture

Quantified Score

Hi-index	0.00

Visualization

Abstract

The Godson project is the first attempt to design high performance general-purpose microprocessors in China. This paper introduces the microarchitecture of the Godson-2 processor which is a 64-bit, 4-issue, out-of-order execution RISC processor that implements the 64-bit MIPS-like instruction set. The adoption of the aggressive out-of-order execution techniques (such as register mapping, branch prediction, and dynamic scheduling) and cache techniques (such as nonblocking cache, load speculation, dynamic memory disambiguation) helps the Godson-2 processor to achieve high performance even at not so high frequency. The Godson-2 processor has been physically implemented on a 6-metal 0.18µm CMOS technology based on the automatic placing and routing flow with the help of some crafted library cells and macros. The area of the chip is 6,700 micrometers by 6,200 micrometers and the clock cycle at typical corner is 2.3ns.