Pentium Pro Processor Design for Test and Debug
IEEE Design & Test
JIAJIA: A Software DSM System Based on a New Cache Coherence Protocol
HPCN Europe '99 Proceedings of the 7th International Conference on High-Performance Computing and Networking
In-System FPGA Prototyping of an Itanium Microarchitecture
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Microarchitecture of the Godson-2 processor
Journal of Computer Science and Technology
A versatile, low latency HyperTransport core
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
An FPGA-based Pentium® in a complete desktop system
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Proceedings of the 45th annual Design Automation Conference
Intel® atom™ processor core made FPGA-synthesizable
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Journal of Computer Science and Technology
ARM Synthesizable Design with Actel FPGAs: with Mixed-Signal SoC Applications (set 3)
ARM Synthesizable Design with Actel FPGAs: with Mixed-Signal SoC Applications (set 3)
An Enhanced HyperTransport Controller with Cache Coherence Support for Multiple-CMP
NAS '09 Proceedings of the 2009 IEEE International Conference on Networking, Architecture, and Storage
An FPGA Design Project: Creating a PowerPC Subsystem Plus User Logic
IEEE Transactions on Education
Efficient in-system RTL verification and debugging using FPGAs (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
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This paper describes a multi-FPGA based platform for emulating the Loongson-2G micro-processor on different mother boards. This platform is developed targeting at verification and evaluation of the Loongson-2G micro-processor, which is the next generation of Loongson-2 family, composed by one four-issue, out-of-order execution way 64-bit MIPS-compatible processor core named GS464, one 1M byte secondary Cache, one HyperTransport IO interface, one DDR2/3 memory interface and some other low speed IO interfaces. Most parts of this micro-process are mapped into the multi-FPGA based platform which consists two Vertex-5 330 FPGA chips. Semi-custom partitioning tactics within the entire design flow are developed to synthesize the whole designed into the multi-FPGA based platform. Modifications in architectural level are applied to the original architecture of the chip, in order to make it easy to be partitioned into two parts. High speed SEDES of HyperTransport IO link and DDR2/3 memory interface are emulated by using several clocks with different clock phases. To resolve the problem that hard to debug in FPGA system, a method by software probe with help of injected hardware modules in FPGA is developed and used to debug the problem causing by behavior mismatching between the ASIC ram block and the FPGA ram block. Some evaluation work on performance of Loongson-2G is done on this multi-FPGA based platform as pre-silicon test. To the authors' knowledge, there has been no previous work on such a big design used for verification and evaluation.