RAMP: Research Accelerator for Multiple Processors

Authors:
John Wawrzynek;David Patterson;Mark Oskin;Shih-Lien Lu;Christoforos Kozyrakis;James C. Hoe;Derek Chiou;Krste Asanovic
Affiliations:
University of California, Berkeley;University of California, Berkeley;University of Washington;Intel;Stanford University;Carnegie Mellon University;University of Texas at Austin;Massachusetts Institute of Technology
Venue:
IEEE Micro
Year:
2007

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Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications

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Iterative probabilistic performance prediction for multi-application multiprocessor systems

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Automated modeling and emulation of interconnect designs for many-core chip multiprocessors

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Abstract

The RAMP project's goal is to enable the intensive, multidisciplinary innovation that the computing industry will need to tackle the problems of parallel processing. RAMP itself is an open-source, community-developed, FPGA-based emulator of parallel architectures. Its design framework lets a large, collaborative community develop and contribute reusable, composable design modules. Three complete designs--for transactional memory, distributed systems, and distributed-shared memory--demonstrate the platform's potential.