Experiments with the Fresh Breeze tree-based memory model

  • Authors:

  • Jack B. Dennis;Guang R. Gao;Xiao X. Meng

  • Affiliations:

  • Computer Science and Artificial Intelligence Laboratory, MIT, Cambridge, USA 02139;Department of Electrical and Computer Engineering, University of Delaware, Newark, USA 19716;Department of Electrical and Computer Engineering, University of Delaware, Newark, USA 19716

  • Venue:
  • Computer Science - Research and Development
  • Year:
  • 2011

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Abstract

The Fresh Breeze memory model and system architecture is proposed as an approach to achieving significant improvements in massively parallel computation by supporting fine-grain management of memory and processing resources and utilizing a global shared name space for all processors and computation tasks. Memory management and the scheduling of tasks are done by hardware realizations, eliminating nearly all operating system execution cycles for data access, task scheduling and security. In particular, the Fresh Breeze memory model uses trees of fixed-size chunks of memory to represent all data objects, which eliminates data consistency issues and simplifies memory management. Low-cost reference-count garbage collection is used to support modular programming in type-safe programming languages.The main contributions of this paper are: (1) a program exection model for massively parallel computing as the Fresh Breeze application programming interface (API) comprising a radical memory model and a scheme for expressing concurrency; (2) an experimental implementation of the API through simulation using the FAST simulator of the IBM Cyclops 64 many-core chip; (3) simulation results that demonstrate that (a) fine-grain hardware-implemented resource management mechanisms can support massive parallelism and high processor utilization through the latency-hiding properties of multi-tasking; and (b) hardware implementation of a work stealing scheme incorporated in our simulation can effectively distribute tasks over the processors of a many-core parallel computer.