Complete Computer System Simulation: The SimOS Approach
IEEE Parallel & Distributed Technology: Systems & Technology
Asim: A Performance Model Framework
Computer
ACM SIGMETRICS Performance Evaluation Review - Special issue on tools for computer architecture research
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Integrated network interfaces for high-bandwidth TCP/IP
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
FlashCache: a NAND flash memory file cache for low power web servers
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Thermal modeling and management of DRAM memory systems
Proceedings of the 34th annual international symposium on Computer architecture
RiceNIC: a reconfigurable network interface for experimental research and education
Proceedings of the 2007 workshop on Experimental computer science
Energy efficient near-threshold chip multi-processing
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
The interval page table: virtual memory support in real-time and memory-constrained embedded systems
Proceedings of the 20th annual conference on Integrated circuits and systems design
Three-dimensional multiprocessor system-on-chip thermal optimization
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Application-aware snoop filtering for low-power cache coherence in embedded multiprocessors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A power-aware shared cache mechanism based on locality assessment of memory reference for CMPs
MEDEA '07 Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Improving the performance of object-oriented languages with dynamic predication of indirect jumps
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
Quantifying software vulnerability
Proceedings of the 2008 workshop on Radiation effects and fault tolerance in nanometer technologies
An approach for adaptive DRAM temperature and power management
Proceedings of the 22nd annual international conference on Supercomputing
Corona: System Implications of Emerging Nanophotonic Technology
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Improving NAND Flash Based Disk Caches
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Proceedings of the 45th annual Design Automation Conference
A power and temperature aware DRAM architecture
Proceedings of the 45th annual Design Automation Conference
Thermal monitoring mechanisms for chip multiprocessors
ACM Transactions on Architecture and Code Optimization (TACO)
The Journal of Supercomputing
PicoServer: Using 3D stacking technology to build energy efficient servers
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Distributed and low-power synchronization architecture for embedded multiprocessors
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Integrating NAND flash devices onto servers
Communications of the ACM - A Direct Path to Dependable Software
Multi-objective Improvement of Software Using Co-evolution and Smart Seeding
SEAL '08 Proceedings of the 7th International Conference on Simulated Evolution and Learning
An evaluation of the TRIPS computer system
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Producing wrong data without doing anything obviously wrong!
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Modeling of cache access behavior based on Zipf's law
Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture
Accurate system-level performance modeling and workload characterization for mobile internet devices
Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture
MC-Sim: an efficient simulation tool for MPSoC designs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Mini-rank: Adaptive DRAM architecture for improving memory power efficiency
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Reconfigurable energy efficient near threshold cache architectures
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
A light-weight fairness mechanism for chip multiprocessor memory systems
Proceedings of the 6th ACM conference on Computing frontiers
Core monitors: monitoring performance in multicore processors
Proceedings of the 6th ACM conference on Computing frontiers
Fast switching of threads between cores
ACM SIGOPS Operating Systems Review
ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices
Proceedings of the 36th annual international symposium on Computer architecture
End-to-end performance forecasting: finding bottlenecks before they happen
Proceedings of the 36th annual international symposium on Computer architecture
ACM SIGARCH Computer Architecture News
ACM SIGARCH Computer Architecture News
Instruction Cache Tuning for Embedded Multitasking Applications
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
Predict and act: dynamic thermal management for multi-core processors
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
A high-performance low-power nanophotonic on-chip network
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Low-power inter-core communication through cache partitioning in embedded multiprocessors
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Reconfigurable Multicore Server Processors for Low Power Operation
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
MPTLsim: a simulator for X86 multicore processors
Proceedings of the 46th Annual Design Automation Conference
Spectrum: a hybrid nanophotonic-electric on-chip network
Proceedings of the 46th Annual Design Automation Conference
PDRAM: a hybrid PRAM and DRAM main memory system
Proceedings of the 46th Annual Design Automation Conference
Full-system simulation of distributed memory multicomputers
Cluster Computing
Segment gating for static energy reduction in Networks-on-Chip
Proceedings of the 2nd International Workshop on Network on Chip Architectures
Multiscale thermal analysis for nanometer-scale integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
EazyHTM: eager-lazy hardware transactional memory
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Proactive transaction scheduling for contention management
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Preemptive virtual clock: a flexible, efficient, and cost-effective QOS scheme for networks-on-chip
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Light speed arbitration and flow control for nanophotonic interconnects
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Low-power snoop architecture for synchronized producer-consumer embedded multiprocessing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Flexible architectural support for fine-grain scheduling
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
A multi-level approach to reduce the impact of NBTI on processor functional units
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Avoiding cache thrashing due to private data placement in last-level cache for manycore scaling
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Dynamic warp subdivision for integrated branch and memory divergence tolerance
Proceedings of the 37th annual international symposium on Computer architecture
Using hardware vulnerability factors to enhance AVF analysis
Proceedings of the 37th annual international symposium on Computer architecture
An approach for adaptive DRAM temperature and power management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms
Proceedings of the 47th Design Automation Conference
Quantifying and coping with parametric variations in 3D-stacked microarchitectures
Proceedings of the 47th Design Automation Conference
A framework for optimizing thermoelectric active cooling systems
Proceedings of the 47th Design Automation Conference
Power-efficient variation-aware photonic on-chip network management
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Energy efficient proactive thermal management in memory subsystem
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Adaptive multi-threading for dynamic workloads in embedded multiprocessors
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimization of an on-chip active cooling system based on thin-film thermoelectric coolers
Proceedings of the Conference on Design, Automation and Test in Europe
Using non-volatile memory to save energy in servers
Proceedings of the Conference on Design, Automation and Test in Europe
Latency criticality aware on-chip communication
Proceedings of the Conference on Design, Automation and Test in Europe
Accurate direct and indirect on-chip temperature sensing for efficient dynamic thermal management
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Cool and save: cooling aware dynamic workload scheduling in multi-socket CPU systems
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Netrace: dependency-driven trace-based network-on-chip simulation
Proceedings of the Third International Workshop on Network on Chip Architectures
Lyrebird: assigning meanings to machines
SSV'10 Proceedings of the 5th international conference on Systems software verification
STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Low-cost and energy-efficient distributed synchronization for embedded multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low-power DSP for wireless communications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MemScale: active low-power modes for main memory
Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems
Exploring circuit timing-aware language and compilation
Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems
RMS-TM: a comprehensive benchmark suite for transactional memory systems
Proceedings of the 2nd ACM/SPEC International Conference on Performance engineering
A workload-adaptive and reconfigurable bus architecture for multicore processors
International Journal of Reconfigurable Computing
The structural simulation toolkit
ACM SIGMETRICS Performance Evaluation Review - Special issue on the 1st international workshop on performance modeling, benchmarking and simulation of high performance computing systems (PMBS 10)
ACM SIGMETRICS Performance Evaluation Review - Special issue on the 1st international workshop on performance modeling, benchmarking and simulation of high performance computing systems (PMBS 10)
A statistical performance model of the opteron processor
ACM SIGMETRICS Performance Evaluation Review - Special issue on the 1st international workshop on performance modeling, benchmarking and simulation of high performance computing systems (PMBS 10)
ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
Iris: A hybrid nanophotonic network design for high-performance and low-power on-chip communication
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Run-time energy management of manycore systems through reconfigurable interconnects
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
A majority-based control scheme for way-adaptable caches
Facing the multicore-challenge
Power-aware dynamic cache partitioning for CMPs
Transactions on high-performance embedded architectures and compilers III
Petri net based performance modeling for effective DVFS for multithreaded programs
Proceedings of the 2011 ACM Symposium on Applied Computing
A majority-based control scheme for way-adaptable caches
Facing the multicore-challenge
From plasma to beefarm: design experience of an FPGA-based multicore prototype
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Mind the gap: reconnecting architecture and OS research
HotOS'13 Proceedings of the 13th USENIX conference on Hot topics in operating systems
Page placement in hybrid memory systems
Proceedings of the international conference on Supercomputing
Reducing Network-on-Chip energy consumption through spatial locality speculation
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees
Proceedings of the 38th annual international symposium on Computer architecture
The role of optics in future high radix switch design
Proceedings of the 38th annual international symposium on Computer architecture
Evaluation of dynamic voltage and frequency scaling for stream programs
Proceedings of the 8th ACM International Conference on Computing Frontiers
ACM SIGARCH Computer Architecture News
Proceedings of the 48th Design Automation Conference
A case for NEMS-based functional-unit power gating of low-power embedded microprocessors
Proceedings of the 48th Design Automation Conference
Proceedings of the 48th Design Automation Conference
Using runtime activity to dynamically filter out inefficient data prefetches
Euro-Par'11 Proceedings of the 17th international conference on Parallel processing - Volume Part I
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Economic learning for thermal-aware power budgeting in many-core architectures
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A latency simulator for many-core systems
Proceedings of the 44th Annual Simulation Symposium
Sniper: exploring the level of abstraction for scalable and accurate parallel multi-core simulation
Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis
An FPGA-based scalable simulation accelerator for tile architectures
ACM SIGARCH Computer Architecture News
On the simulation of large-scale architectures using multiple application abstraction levels
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
VSim: Simulating multi-server setups at near native hardware speed
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
Memory access cycle and the measurement of memory systems
Proceedings of the second international workshop on Performance modeling, benchmarking and simulation of high performance computing systems
Efficient memory management of a hierarchical and a hybrid main memory for MN-MATE platform
Proceedings of the 2012 International Workshop on Programming Models and Applications for Multicores and Manycores
A fair thread-aware memory scheduling algorithm for chip multiprocessor
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
Idempotent processor architecture
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
System-level integrated server architectures for scale-out datacenters
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Heterogeneous integration to simplify many-core architecture simulations
Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
A high performance adaptive miss handling architecture for chip multiprocessors
Transactions on High-Performance Embedded Architectures and Compilers IV
Low-Overhead, high-speed multi-core barrier synchronization
HiPEAC'10 Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers
DIEF: an accurate interference feedback mechanism for chip multiprocessor memory systems
HiPEAC'10 Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers
Fine-Grained timing using genetic programming
EuroGP'10 Proceedings of the 13th European conference on Genetic Programming
Link-time optimization for power efficiency in a tagless instruction cache
CGO '11 Proceedings of the 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization
An optimized multicore cache coherence design for exploiting communication locality
Proceedings of the great lakes symposium on VLSI
Memory-based computing for performance and energy improvement in multicore architectures
Proceedings of the great lakes symposium on VLSI
Proceedings of the 49th Annual Design Automation Conference
Boosting single thread performance in mobile processors via reconfigurable acceleration
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
ScalableCore system: a scalable many-core simulator by employing over 100 FPGAs
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Real-time network-on-chip simulation modeling
Proceedings of the 5th International ICST Conference on Simulation Tools and Techniques
Improvements to the structural simulation toolkit
Proceedings of the 5th International ICST Conference on Simulation Tools and Techniques
Multiple sub-row buffers in DRAM: unlocking performance and energy improvement opportunities
Proceedings of the 26th ACM international conference on Supercomputing
Locality & utility co-optimization for practical capacity management of shared last level caches
Proceedings of the 26th ACM international conference on Supercomputing
TAP: token-based adaptive power gating
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
MultiScale: memory system DVFS with multiple memory controllers
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
A charge pump based receiver circuit for voltage scaled interconnect
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Probabilistic shared cache management (PriSM)
Proceedings of the 39th Annual International Symposium on Computer Architecture
XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
Transactional prefetching: narrowing the window of contention in hardware transactional memory
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
Reducing NBTI-induced processor wearout by exploiting the timing slack of instructions
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
APC: a performance metric of memory systems
ACM SIGMETRICS Performance Evaluation Review
Resource-bounded multicore emulation using Beefarm
Microprocessors & Microsystems
Per-thread cycle accounting in multicore processors
ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers
CRAW/P: a workload partition method for the efficient parallel simulation of manycores
Euro-Par'12 Proceedings of the 18th international conference on Parallel Processing
Efficient Reuse Distance Analysis of Multicore Scaling for Loop-Based Parallel Programs
ACM Transactions on Computer Systems (TOCS)
A Simulator for Large-Scale Parallel Computer Architectures
International Journal of Distributed Systems and Technologies
ACM Transactions on Architecture and Code Optimization (TACO)
CoScale: Coordinating CPU and Memory System DVFS in Server Systems
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
A survey on cache tuning from a power/energy perspective
ACM Computing Surveys (CSUR)
Fault tolerance for multi-threaded applications by leveraging hardware transactional memory
Proceedings of the ACM International Conference on Computing Frontiers
RFiof: an RF approach to I/O-pin and memory controller scalability for off-chip memories
Proceedings of the ACM International Conference on Computing Frontiers
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
FaulTM: error detection and recovery using hardware transactional memory
Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting subarrays inside a bank to improve phase change memory performance
Proceedings of the Conference on Design, Automation and Test in Europe
On-the-fly verification of memory consistency with concurrent relaxed scoreboards
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
CPU transparent protection of OS kernel and hypervisor integrity with programmable DRAM
Proceedings of the 40th Annual International Symposium on Computer Architecture
ZSim: fast and accurate microarchitectural simulation of thousand-core systems
Proceedings of the 40th Annual International Symposium on Computer Architecture
Modeling communication software execution for accurate simulation of distributed systems
Proceedings of the 2013 ACM SIGSIM conference on Principles of advanced discrete simulation
Locality-aware task management for unstructured parallelism: a quantitative limit study
Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures
Co-tuning of a hybrid electronic-optical network for reducing energy consumption in embedded CMPs
Proceedings of the First International Workshop on Many-core Embedded Systems
Enhancing NBTI recovery in SRAM arrays through recovery boosting
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Return data interleaving for multi-channel embedded CMPs systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automated generation of directed tests for transition coverage in cache coherence protocols
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
On ESL verification of memory consistency for system-on-chip multiprocessing
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
TagTM - accelerating STMs with hardware tags for fast meta-data access
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
NBTI mitigation by optimized NOP assignment and insertion
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
TempoMP: integrated prediction and management of temperature in heterogeneous MPSoCs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Analysis and runtime management of 3D systems with stacked DRAM for boosting energy efficiency
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
MAPG: memory access power gating
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Low-power, low-storage-overhead chipkill correct via multi-line error correction
SC '13 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
Adaptive communication mechanism for accelerating MPI functions in NoC-based multicore processors
ACM Transactions on Architecture and Code Optimization (TACO)
VGTS: variable granularity transactional snoop
Euro-Par'13 Proceedings of the 19th international conference on Parallel Processing
CoMETC: Coordinated management of energy/thermal/cooling in servers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Transactions on Embedded Computing Systems (TECS)
Dynamic bandwidth scaling for embedded DSPs with 3D-stacked DRAM and wide I/Os
Proceedings of the International Conference on Computer-Aided Design
System performance evaluation by combining RTC and VHDL simulation: A case study on NICs
Journal of Systems Architecture: the EUROMICRO Journal
Exascale design space exploration and co-design
Future Generation Computer Systems
VBON: Toward efficient on-chip networks via hierarchical virtual bus
Microprocessors & Microsystems
Unified reliability estimation and management of NoC based chip multiprocessors
Microprocessors & Microsystems
A novel architecture for ahead branch prediction
Frontiers of Computer Science: Selected Publications from Chinese Universities
Using Dynamic Runtime Testing for Rapid Development of Architectural Simulators
International Journal of Parallel Programming
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Developed specifically to enable research in TCP/IP networking, the M5 simulator provides features necessary for simulating networked hosts, including full-system capability, a detailed I/O subsystem, and the ability to simulate multiple networked systems deterministically. M5's usefulness as a general-purpose architecture simulator and its liberal open-source license have led to its adoption by several academic and commercial groups.