Embedded DRAM technology opportunities and challenges
IEEE Spectrum
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Memory controller policies for DRAM power management
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Hardware and Software Techniques for Controlling DRAM Power Modes
IEEE Transactions on Computers
Low-energy off-chip SDRAM memory systems for embedded applications
ACM Transactions on Embedded Computing Systems (TECS)
Memory Controller Optimizations for Web Servers
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Bridging the Processor-Memory Performance Gapwith 3D IC Technology
IEEE Design & Test
The M5 Simulator: Modeling Networked Systems
IEEE Micro
Thermal modeling and management of DRAM memory systems
Proceedings of the 34th annual international symposium on Computer architecture
An approach for adaptive DRAM temperature and power management
Proceedings of the 22nd annual international conference on Supercomputing
A power and temperature aware DRAM architecture
Proceedings of the 45th annual Design Automation Conference
An efficient quality-aware memory controller for multimedia platform SoC
IEEE Transactions on Circuits and Systems for Video Technology
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High-performance DRAMs are providing increasing memory access bandwidth to processors, which is leading to high power consumption and operating temperature in DRAM chips. In this paper, we propose a customized low-power technique for high-performance DRAM systems to improve DRAM page hit rate by buffering write operations that may incur page misses. This approach reduces DRAM system power consumption and temperature without any performance penalty. We combine the throughput-aware page-hit-aware write buffer (TAP) with low-power-state-based techniques for further power and temperature reduction, namely, TAP-low. Our experiments show that a system with TAP-low could reduce the total DRAM power consumption by up to 68.6% (19.9% on average). The steady-state temperature can be reduced by as much as 7.84 °C and 2.55°C on average across eight representative workloads.