Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs
Proceedings of the conference on Design, automation and test in Europe
Automatic Code Mapping on an Intelligent Memory Architecture
IEEE Transactions on Computers
Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test
Journal of Electronic Testing: Theory and Applications
Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs
IEEE Transactions on Computers
In-memory Parallelism for Database Workloads
Euro-Par '02 Proceedings of the 8th International Euro-Par Conference on Parallel Processing
The DIVA Emulator: Accelerating Architecture Studies for PIM-Based Systems
IMS '00 Revised Papers from the Second International Workshop on Intelligent Memory Systems
Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips
IMS '00 Revised Papers from the Second International Workshop on Intelligent Memory Systems
Adaptively Mapping Code in an Intelligent Memory Architecture
IMS '00 Revised Papers from the Second International Workshop on Intelligent Memory Systems
Configurable parallel memory architecture for multimedia computers
Journal of Systems Architecture: the EUROMICRO Journal
Programming the FlexRAM parallel intelligent memory system
Proceedings of the ninth ACM SIGPLAN symposium on Principles and practice of parallel programming
Data forwarding through in-memory precomputation threads
Proceedings of the 18th annual international conference on Supercomputing
Process optimization and characterization of deep metal-junction contact
Microelectronic Engineering
Challenges in Embedded Memory Design and Test
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System
Journal of VLSI Signal Processing Systems
Challenges and future directions for the scaling of dynamic random-access memory (DRAM)
IBM Journal of Research and Development
Embedded DRAM: technology platform for the Blue Gene/L chip
IBM Journal of Research and Development
An approach for adaptive DRAM temperature and power management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Embedding dynamic RAMs will give system designers large amounts of high-bandwidth, high-performance memory to apply to completely new functions. Although embedding DRAM allows for a new dimension in large-scale integration, the path to success is not smooth. Redesigning at the system level is a must for exploiting the wide memory widths to obtain the performance available-merely mapping existing designs results in larger chips with lower yields in more expensive technologies. The creative designer, who innovates and redesigns, will be the winner in the new world of embedded DRAM