A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System

Authors:
Jaffrey Draper;J. Tim Barrett;Jeff Sondeen;Sumit Mediratta;Chang Woo Kang;Ihn Kim;Gokhan Daglikoca
Affiliations:
Information Sciences Institute, University of Southern California, Marina del Rey, USA 90292;Information Sciences Institute, University of Southern California, Marina del Rey, USA 90292;Information Sciences Institute, University of Southern California, Marina del Rey, USA 90292;Information Sciences Institute, University of Southern California, Marina del Rey, USA 90292;Information Sciences Institute, University of Southern California, Marina del Rey, USA 90292;Information Sciences Institute, University of Southern California, Marina del Rey, USA 90292;Information Sciences Institute, University of Southern California, Marina del Rey, USA 90292
Venue:
Journal of VLSI Signal Processing Systems
Year:
2005

Citing 18
Cited 0

Active messages: a mechanism for integrated communication and computation

ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Memory bandwidth limitations of future microprocessors

ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Missing the memory wall: the case for processor/memory integration

ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Active pages: a computation model for intelligent memory

Proceedings of the 25th annual international symposium on Computer architecture
Computer architecture (2nd ed.): a quantitative approach

Computer architecture (2nd ed.): a quantitative approach
Performance of image and video processing with general-purpose processors and media ISA extensions

ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Microservers: a new memory semantics for massively parallel computing

ICS '99 Proceedings of the 13th international conference on Supercomputing
Embedded DRAM technology opportunities and challenges

IEEE Spectrum
Mapping irregular applications to DIVA, a PIM-based data-intensive architecture

SC '99 Proceedings of the 1999 ACM/IEEE conference on Supercomputing
Exploiting superword level parallelism with multimedia instruction sets

PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
The architecture of the DIVA processing-in-memory chip

ICS '02 Proceedings of the 16th international conference on Supercomputing
Processing in Memory: The Terasys Massively Parallel PIM Array

Computer
Computational RAM: Implementing Processors in Memory

IEEE Design & Test
Subword Parallelism with MAX-2

IEEE Micro
Implementation of a 32-bit RISC Processor for the Data-Intensive Architecture Processing-In-Memory Chip

ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Parallelizing Applications into Silicon

FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Impulse: Building a Smarter Memory Controller

HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
FlexRAM: Toward an Advanced Intelligent Memory System

ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

The Data-Intensive Architecture (DIVA) system employs Processing-In-Memory (PIM) chips as smart-memory coprocessors. This architecture exploits inherent memory bandwidth both on chip and across the system to target several classes of bandwidth-limited applications, including multimedia applications and pointer-based and sparse-matrix computations. The DIVA project has built a prototype development system using PIM chips in place of standard DRAMs to demonstrate these concepts. We have recently ported several demonstration kernels to this platform and have exhibited a speedup of 35X on a matrix transpose operation.This paper focuses on the 32-bit scalar and 256-bit WideWord integer processing components of the first DIVA prototype PIM chip, which was fabricated in TSMC 0.18 驴m technology. In conjunction with other publications, this paper demonstrates that impressive gains can be achieved with very little "smart" logic added to memory devices. A second PIM prototype that includes WideWord floating-point capability is scheduled to tape out in August 2003.