Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Industrial evaluation of DRAM tests
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Embedded DRAM technology opportunities and challenges
IEEE Spectrum
Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs
Proceedings of the conference on Design, automation and test in Europe
The Behavior and Testing Implications of CMOS IC Logic Gate Open Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Impact of memory cell array bridges on the faulty behavior in embedded DRAMs
ATS '00 Proceedings of the 9th Asian Test Symposium
March LA: a test for linked memory faults
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Functional Memory Faults: A Formal Notation and a Taxonomy
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Industrial Evaluation of Stress Combinations for March Tests applied to SRAMs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Enhancing Yield at the End of the Technology Roadmap
IEEE Design & Test
Techniques for Disturb Fault Collapsing
Journal of Electronic Testing: Theory and Applications
Test set development for cache memory in modern microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Genetic defect based march test generation for SRAM
EvoApplications'11 Proceedings of the 2011 international conference on Applications of evolutionary computation - Volume Part II
| Hi-index | 14.98 |
Spot defects in memory devices are caused by imperfections in the fabrication process of these devices. In order to analyze the faulty effect of spot defects on the memory behavior, simulations have been performed on an electrical model of the memory in which the defects are injected, causing opens, shorts, or bridges. In this paper, simulation is used to analyze the faulty behavior of embedded DRAM (eDRAM) devices produced by Infineon Technologies. The paper applies the new approach of fault primitives to perform this analysis. The analysis shows the existence of most traditional memory fault models and establishes new ones. The paper also investigates the concept of dynamic faulty behavior and establishes its importance for eDRAMs. Conditions to test the newly established fault models, together with a test, are also given.