Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Structured Logic Testing
Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs
IEEE Transactions on Computers
Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Yield Increase of VLSI after Redundancy-Repairing
ATS '01 Proceedings of the 10th Asian Test Symposium
DiCER: distributed and cost-effective redundancy for variation tolerance
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Encountering gate oxide breakdown with shadow transistors to increase reliability
Proceedings of the 21st annual symposium on Integrated circuits and system design
Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdown
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
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Editors' note: Scaled manufacturing technologies require advanced techniques for improving device reliability and production yield.This article presents a transistor-level redundancy technique for manufacturing devices with low vulnerability and improving yieldin future circuits. The technique relies on appropriate design style selection and controlled redundancy to achieve area and power trade-offs. 驴Dimitris Gizopoulos, University of Piraeus