Probability and Statistics with Reliability, Queuing and Computer Science Applications
Probability and Statistics with Reliability, Queuing and Computer Science Applications
The Vision of Autonomic Computing
Computer
A Detailed Analysis of GOS Defects in MOS Transistors: Testing Implications at Circuit Level
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Techniques for Yield Enhancement of VLSI Adders
ASAP '95 Proceedings of the IEEE International Conference on Application Specific Array Processors
Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short
Journal of Electronic Testing: Theory and Applications
The Impact of Technology Scaling on Lifetime Reliability
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
Enhancing Yield at the End of the Technology Roadmap
IEEE Design & Test
Organic Computing - A New Vision for Distributed Embedded Systems
ISORC '05 Proceedings of the Eighth IEEE International Symposium on Object-Oriented Real-Time Distributed Computing
Adaptive Design for Performance-Optimized Robustness
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
Fault-Tolerant Systems
Design of mixed gates for leakage reduction
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Latch Susceptibility to Transient Faults and New Hardening Approach
IEEE Transactions on Computers
Reliability limits for the gate insulator in CMOS technology
IBM Journal of Research and Development
Increasing lifetime of wireless sensor networks with energy-aware role-changing
SelfMan'06 Proceedings of the Second IEEE international conference on Self-Managed Networks, Systems, and Services
Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdown
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
| Hi-index | 0.00 |
Device scaling has enabled continuous performance increase of integrated circuits. However, severe reliability and yield concerns are arising against the background of nanotechnology. Tradition-ally, most causes and countermeasures were solely considered manufacturing issues, but lately, we have seen a shift towards op-erational reliability issues. Though, besides intense research on soft-errors and system-level approaches very little effort is put into low-level design solutions in order to enhance lifetime reliability. Hence, we demonstrate that redundant transistor insertion does im-prove system reliability significantly as regards Time-Dependent Dielectric Breakdown (TDDB). Furthermore, we introduce an al-gorithm which identifies the transistors being most vulnerable to TDDB. Subsequently, redundant transistors (called shadow transis-tors) are inserted at the previously identified instances. Lastly, we argue for applying high threshold voltage devices for the redundant transistors. Finally, we present results for a set of benchmark cir-cuits and prove the combined approach successful. The enhanced designs were on average 41.8% more reliable compared to the ini-tial designs in respect of TDDB at the price of moderately in-creased power consumption and delay.