Mixed-Vth (MVT) CMOS circuit design methodology for low power applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Low power synthesis of dual threshold voltage CMOS VLSI circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering
IEEE Design & Test
Analysis and minimization techniques for total leakage considering gate oxide leakage
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 2003 international symposium on Low power electronics and design
Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Characterization and modeling of run-time techniques for leakage power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Enhanced leakage reduction Technique by gate replacement
Proceedings of the 42nd annual Design Automation Conference
Encountering gate oxide breakdown with shadow transistors to increase reliability
Proceedings of the 21st annual symposium on Integrated circuits and system design
ULS: A dual-Vth/high-κ nano-CMOS universal level shifter for system-level power management
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Leakage power dissipation is one of the most critical factors for the overall current dissipation and future designs. However, design techniques for the reduction of leakage power should not decrease design performance. Therefore, an enhanced Dual Vth/Dual Tox CMOS ap-proach is presented which applies mixed gates consisting of different transistor types. The paper introduces the new and fundamental idea of different gate types before the various possible configurations are analyzed. This is followed by extraction and exploration of design rules and recommendations. Simulations of modified ISCAS'85 designs show an average leakage reduction of 60% at constant performance compared to raw designs. This corresponds to an additional reduction of 20% compared to previous Dual Vth/Dual Tox CMOS approaches.