Total leakage power optimization with improved mixed gates
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Power reduction techniques for microprocessor systems
ACM Computing Surveys (CSUR)
Design of mixed gates for leakage reduction
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Minimizing leakage: what if every gate could have its individual threshold voltage?
AIAP'07 Proceedings of the 25th conference on Proceedings of the 25th IASTED International Multi-Conference: artificial intelligence and applications
A Structural Customization Approach for Low Power Embedded Systems Design
GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing
Gate oxide leakage and delay tradeoffs for dual-toxcircuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel gate-level NBTI delay degradation model with stacking effect
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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Gate oxide tunneling current (I{gate}) is emerging as a key roadblock for device scaling in nanometer-scale CMOS circuits. A practical means to reduce I{gate} is to leverage dual T{ox} processes where non-critical transistors are assigned a thicker T{ox}. In this paper, we generate a leakage/delay tradeoff curve for dual T{ox} circuits, and propose a transistor and pin reordering technique that has a minimal layout impact to further reduce the total leakage current up to 18% and I{gate} up to 26% without incurring any delay penalty.