Transistor sizing issues and tool for multi-threshold CMOS technology
DAC '97 Proceedings of the 34th annual Design Automation Conference
Mixed-Vth (MVT) CMOS circuit design methodology for low power applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Low power synthesis of dual threshold voltage CMOS VLSI circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Proceedings of the 2003 international symposium on Low power electronics and design
Low power gate-level design with mixed-Vth (MVT) techniques
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
VLSI Design Challenges for Gigascale Integration
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Reducing Leakage with Mixed-V_th (MVT)
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
High-speed, low-leakage integrated circuits: An evolutionary algorithm perspective
Journal of Systems Architecture: the EUROMICRO Journal
Biologically-Inspired optimization of circuit performance and leakage: a comparative study
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
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Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness of gate oxide layer Tox. In this paper, we propose a new method that combines approaches of Dual Threshold CMOS (DTCMOS), mixed-Tox CMOS, and pin-reordering. As the reduction of leakage leads to an increase of gate delay, our purpose is the reduction of total leakage at constant design performance. We modified a given technology and developed a library with a new mixed gate type. Compared to the case where all devices are set to high performance, our approach achieves an average leakage reduction of 65%, whereas design performance stays constant.