Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mixed-Vth (MVT) CMOS circuit design methodology for low power applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Low power synthesis of dual threshold voltage CMOS VLSI circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Proceedings of the 39th annual Design Automation Conference
Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering
IEEE Design & Test
Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses
IEEE Design & Test
Total leakage power optimization with improved mixed gates
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
High-speed, low-leakage integrated circuits: An evolutionary algorithm perspective
Journal of Systems Architecture: the EUROMICRO Journal
Biologically-Inspired optimization of circuit performance and leakage: a comparative study
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
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The reduction of leakage power has become an important issue for high performance designs. One way to achieve low-leakage and high performance designs is the use of multi-threshold techniques. In this paper, a new mixed-Vth (MVT) CMOS design technique is proposed, which uses different threshold voltages within a logic gate. This new technique allows the reduction of leakage power, while the performance stays constant. A set of algorithms is given assigning optimal distribution of gates. Results indicate that the new MVT approach can provide up to 40% leakage reduction by constant performance compared to dual-Vth (DVT) gate-level techniques.