Design and optimization of dual-threshold circuits for low-voltage low-power applications

Authors:
Liqiong Wei;Zhanping Chen;Kaushik Roy;Mark C. Johnson;Yibin Ye;Vivek K. De
Affiliations:
Purdue Univ., West Lafayette, IN;Purdue Univ., West Lafayette, IN;Purdue Univ., West Lafayette, IN;Purdue Univ., West Lafayette, IN;Intel Corp., Hillsboro, OR;Intel Corp., Hillsboro, OR
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
1999

Citing 0
Cited 73

Mixed-Vth (MVT) CMOS circuit design methodology for low power applications

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Leakage control with efficient use of transistor stacks in single threshold CMOS

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Dual-VT SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13 μm technology generation

ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Cell selection from technology libraries for minimizing power

Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Future performance challenges in nanometer design

Proceedings of the 38th annual Design Automation Conference
Synthesis of low-leakage PD-SOI circuits with body-biasing

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
On gate level power optimization using dual-supply voltages

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On effective IDDQ Testing of low-voltage CMOS circuits using leakage control techniques

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage control with efficient use of transistor stacks in single threshold CMOS

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of dual-Vt SRAM cells with full-swing single-ended bit line sensing for on-chip cache

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique

Proceedings of the 39th annual Design Automation Conference
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors

Proceedings of the 39th annual Design Automation Conference
Logic synthesis for low power

Logic Synthesis and Verification
IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions

IEEE Design & Test
Subthreshold leakage modeling and reduction techniques

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Sub-90nm technologies: challenges and opportunities for CAD

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Energy-efficient skewed static logic with dual Vt: design and synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Low Power Solution for Wireless Applications

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Quality of EDA CAD Tools: Definitions, Metrics and Directions

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Selective gate-length biasing for cost-effective runtime leakage control

Proceedings of the 41st annual Design Automation Conference
Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Post-layout leakage power minimization based on distributed sleep transistor insertion

Proceedings of the 2004 international symposium on Low power electronics and design
Approaches to run-time and standby mode leakage reduction in global buses

Proceedings of the 2004 international symposium on Low power electronics and design
Low power gate-level design with mixed-Vth (MVT) techniques

SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Analytical models for leakage power estimation of memory array structures

Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
On Statistical Timing Analysis with Inter- and Intra-Die Variations

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Characterization and modeling of run-time techniques for leakage power reduction

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Challenges and design choices in nanoscale CMOS

ACM Journal on Emerging Technologies in Computing Systems (JETC)
A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Technology mapping for low leakage power and high speed with hot-carrier effect consideration

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Achieving continuous VT performance in a dual VT process

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Dual-Vt Design of FPGAs for Subthreshold Leakage Tolerance

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Test Consideration for Nanometer-Scale CMOS Circuits

IEEE Design & Test
An analytical state dependent leakage power model for FPGAs

Proceedings of the conference on Design, automation and test in Europe: Proceedings
Enabling fine-grain leakage management by voltage anchor insertion

Proceedings of the conference on Design, automation and test in Europe: Proceedings
Low-power design techniques for scaled technologies

Integration, the VLSI Journal - Special issue: Low-power design techniques
A case study: power and performance improvement of a chip multiprocessor for transaction processing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing driven power gating

Proceedings of the 43rd annual Design Automation Conference
Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits

Proceedings of the 2006 international symposium on Low power electronics and design
Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations

CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Digital Circuit Optimization via Geometric Programming

Operations Research
Soft-well digital circuit design

Proceedings of the 20th annual conference on Integrated circuits and systems design
Minimizing the dynamic and sub-threshold leakage power consumption using least leakage vector-assisted technology mapping

Integration, the VLSI Journal
Minimizing leakage power in sequential circuits by using mixed Vt flip-flops

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Design of dual threshold voltages asynchronous circuits

Proceedings of the 13th international symposium on Low power electronics and design
A new algorithm for simultaneous gate sizing and threshold voltage assignment

Proceedings of the 2009 international symposium on Physical design
Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits

Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
GPU-based parallelization for fast circuit optimization

Proceedings of the 46th Annual Design Automation Conference
Low-power design techniques for scaled technologies

Integration, the VLSI Journal - Special issue: Low-power design techniques
Sleep transistor sizing for leakage power minimization considering charge balancing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new algorithm for simultaneous gate sizing and threshold voltage assignment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ULS: A dual-Vth/high-κ nano-CMOS universal level shifter for system-level power management

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Dual-Vth leakage reduction with fast clock skew scheduling enhancement

Proceedings of the Conference on Design, Automation and Test in Europe
Temperature-insensitive dual-Vth synthesis for nanometer CMOS technologies under inverse temperature dependence

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical leakage power optimization of asynchronous circuits considering process variations

PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Lagrangian relaxation for gate implementation selection

Proceedings of the 2011 international symposium on Physical design
GPU-Based Parallelization for Fast Circuit Optimization

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Cell-based leakage power reduction priority (CBLPRP) optimization methodology for designing SOC applications using MTCMOS technique

PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
An optimization mechanism intended for static power reduction using dual-Vth technique

Journal of Electrical and Computer Engineering
Discrete sizing for leakage power optimization in physical design: A comparative study

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Triple-threshold static power minimization in high-level synthesis of VLSI CMOS

PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
A magnetic tunnel junction based zero standby leakage current retention flip-flop

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation-aware supply voltage assignment for simultaneous power and aging optimization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Post-synthesis leakage power minimization

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Variability-aware architecture level optimization techniques for robust nanoscale chip design

Computers and Electrical Engineering

Quantified Score

Hi-index	0.00

Visualization

Abstract

Reduction in leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, we use the dual-threshold technique to reduce leakage power by assigning a high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path(s). In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high-threshold voltage. A general leakage current model which has been verified by HSPICE simulations is used to estimate leakage power. Results show that the dual-threshold technique is good for leakage power reduction during both standby and active modes. For some ISCAS benchmark circuits, the leakage power can be reduced by more than 80%. The total active power saving can be around 50% and 20% at low- and high-switching activities, respectively.