Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Life is CMOS: why chase the life after?
Proceedings of the 39th annual Design Automation Conference
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
Proceedings of the 41st annual Design Automation Conference
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
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Process parameter variations cause large changes in the delay and the leakage power consumption of scaled nanometer CMOS circuits. In this paper, the problem of leakage power variation minimization in the presence of spatially correlated across-die process variations is addressed. It is shown that with minimal impact on delay, the placement of low-Vt gates in a layout can be performed in such a way to maximize the yield for a specified leakage power upper bound. For the obtained placement of low Vt gates, the layout can then be optimized for other important criteria such as wire length. Simulation of across-die variations for ISCAS benchmarks is performed and guidelines for distributing the low-Vt gates across the die are developed.