Impact of process variations on pulsed flip-flops: yield improving circuit-level techniques and comparative analysis

Authors:
Marco Lanuzza;Raffaele De Rose;Fabio Frustaci;Stefania Perri;Pasquale Corsonello
Affiliations:
Departement of Electronics, Computer Science and Systems, University of Calabria, Rende, CS;Departement of Electronics, Computer Science and Systems, University of Calabria, Rende, CS;Departement of Electronics, Computer Science and Systems, University of Calabria, Rende, CS;Departement of Electronics, Computer Science and Systems, University of Calabria, Rende, CS;Departement of Electronics, Computer Science and Systems, University of Calabria, Rende, CS
Venue:
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Year:
2010

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Abstract

Process variations cause unpredictability in speed and power characteristics of nanometer CMOS circuits impacting the timing and energy yields. In this paper, transistor reordering and dual-Vth techniques are evaluated regarding their efficiency in mitigating the impact of process variations on a set of pulsed flip-flops. It is shown that the conjunct use of the above mentioned techniques can improve delay, energy and EDP yields more than 1.98X, 1.62X and 1.99X times, respectively. The yield optimized flip-flop circuits are also comparatively analyzed to identify the best topologies.