Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
High-performance energy-efficient D-flip-flop circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
New clock-gating techniques for low-power flip-flops
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy
ARVLSI '01 Proceedings of the 2001 Conference on Advanced Research in VLSI
Level conversion for dual-supply systems
Proceedings of the 2003 international symposium on Low power electronics and design
Optimization of scannable latches for low energy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Level conversion for dual-supply systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Slack borrowing in flip-flop based sequential circuits
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Dual-edge triggered storage elements and clocking strategy for low-power systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel high-speed sense-amplifier-based flip-flop
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger
Journal of Electronic Testing: Theory and Applications
Conditional data mapping flip-flops for low-power and high-performance systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Flip-flop energy/performance versus clock slope and impact on the clock network design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
General strategies to design nanometer flip-flops in the energy-delay space
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Physical design aware comparison of flip-flops for high-speed energy-efficient VLSI circuits
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of sequential elements for low power clocking system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 0.00 |