Power optimal buffered clock tree design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Low power, testable dual edge triggered flip-flops
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Clock Distribution Methodology for PowerPC™Microprocessors
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Clock distribution using multiple voltages
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Skew-tolerant circuit design
Analysis and design of low-energy flip-flops
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Statistical clock skew modeling with data delay variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Digital System Clocking: High-Performance and Low-Power Aspects
Digital System Clocking: High-Performance and Low-Power Aspects
Clustering and load balancing for buffered clock tree synthesis
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies
Proceedings of the 2003 international symposium on Low power electronics and design
Clocking and clocked storage elements in a multi-gigahertz environment
IBM Journal of Research and Development
High-performance and low-power conditional discharge flip-flop
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dual-edge triggered storage elements and clocking strategy for low-power systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-Performance Energy-Efficient Microprocessor Design (Series on Integrated Circuits and Systems)
High-Performance Energy-Efficient Microprocessor Design (Series on Integrated Circuits and Systems)
Design for Manufacturability and Statistical Design: A Comprehensive Approach
Design for Manufacturability and Statistical Design: A Comprehensive Approach
Impact of supply voltage variations on full adder delay: analysis and comparison
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
General strategies to design nanometer flip-flops in the energy-delay space
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Understanding the effect of process variations on the delay of static and domino logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Estimation of average switching activity in combinational logic circuits using symbolic simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
General strategies to design nanometer flip-flops in the energy-delay space
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Physical design aware comparison of flip-flops for high-speed energy-efficient VLSI circuits
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Ring oscillators for functional and delay test of latches and flip-flops
Proceedings of the 24th symposium on Integrated circuits and systems design
From energy-delay metrics to constraints on the design of digital circuits
International Journal of Circuit Theory and Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, the influence of the clock slope on the speed of various classes of flip-flops (FFs) and on the overall energy dissipation of both FFs and clock domain buffers is analyzed. Analysis shows that an optimum clock slope exists, which minimizes the energy spent in a clock domain. Results show that the clock slope requirement can be relaxed with respect to traditional assumptions, leading up to 30 ÷ 40 % energy savings and at a very small speed performance penalty. The effectiveness of the clock slope optimization is discussed in detail for the existing classes of FFs. The impact of such an optimization in terms of additive skew and jitter contributions is discussed, together to the analysis of the impact of technology scaling. Extensive post-layout simulations on a 65-nm CMOS technology are performed to check the validity of the underlying assumptions and approximations.