Increasing processor performance by implementing deeper pipelines
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Skewed CMOS: noise-tolerant high-performance low-power static circuit family
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic addressing memory arrays with physical locality
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Energy and Performance Models for Clocked and Asynchronous Communication
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Test Methodology for the McKinley Processor
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Testing Clock Distribution Circuits Using an Analytic Signal Method
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Token Scan Architecture for Low Power Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Reducing translation lookaside buffer active power
Proceedings of the 2003 international symposium on Low power electronics and design
Analysis of blocking dynamic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing pipeline energy demands with local DVS and dynamic retiming
Proceedings of the 2004 international symposium on Low power electronics and design
Clocking and clocked storage elements in a multi-gigahertz environment
IBM Journal of Research and Development
Delay insertion method in clock skew scheduling
Proceedings of the 2005 international symposium on Physical design
A 65-nm pulsed latch with a single clocked transistor
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis
Proceedings of the 37th annual international symposium on Computer architecture
Flip-flop energy/performance versus clock slope and impact on the clock network design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design
Proceedings of the 48th Design Automation Conference
Automated design of cryptographic devices resistant to multiple side-channel attacks
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
| Hi-index | 0.00 |