A method of delay fault test generation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Skew-tolerant circuit design
ATPG for Heat Dissipation Minimization During Test Application
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
An Input Control Technique for Power Reduction in Scan Circuits During Test Application
ATS '99 Proceedings of the 8th Asian Test Symposium
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
20.3 A Test Pattern Generation Methodology for Low-Power Consumption
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A Test Vector Inhibiting Technique for Low Energy BIST Design
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Low Power Testing of VLSI Circuits: Problems and Solutions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Addressable Test Ports An Approach to Testing Embedded Cores
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a novel scan architecture for low-power testing, which employs the techniques of multiphase clocking, token ring, and clockgating. Whenthe multiphase clocking technique is directly employedto a scan chain, inter-phase skews and large routingarea wil be the problems. We develop a token scancell design to address these problems. To reduce thepower dissipation due to the clock and scan-in datatrees, we propose a novel clockgating technique thattakes the advantage of the regularity and periodicityof the token scan chain. Combining the three techniques, the token scan architecture can efficiently reduce the data transitions in the scan circuits as wellas the switching activity in both the clock and thescan-in data trees. From experiments, more than 95%of power reduction can be achieved for most circuitswith long scan chains.