Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
A delay test system for high speed logic LSI's
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Test generation for MOS circuits using D-algorithm
DAC '83 Proceedings of the 20th Design Automation Conference
Automatic test generation for stuck-open faults in CMOS VLSI
DAC '81 Proceedings of the 18th Design Automation Conference
A deterministic approach to adjacency testing for delay faults
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
At-speed delay testing of synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Delay fault test generation for scan/hold circuits using Boolean expressions
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Correlation-reduced scan-path design to improve delay fault coverage
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A quantitative measure of robustness for delay fault testing
EURO-DAC '92 Proceedings of the conference on European design automation
A Scan-BIST Structure to Test Delay Faults in Sequential Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Journal of Electronic Testing: Theory and Applications
Delay-Fault Diagnosis by Critical-Path Tracing
IEEE Design & Test
Generating Tests for Delay Faults in Nonscan Circuits
IEEE Design & Test
Test Generation for Path Delay Faults Using Binary Decision Diagrams
IEEE Transactions on Computers
Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
Gate delay fault test generation for non-scan circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Analyzing and improving delay defect tolerance in pipelined combinational circuits
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
A Token Scan Architecture for Low Power Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Delay Testing of SOI Circuits: Challenges with the History Effect
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Controllability of Static CMOS Circuits for Timing Characterization
Journal of Electronic Testing: Theory and Applications
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Fastpath: a path-delay test generator for standard scan designs
ITC'94 Proceedings of the 1994 international conference on Test
On path delay testing in a standard scan environment
ITC'94 Proceedings of the 1994 international conference on Test
Fixed-state tests for delay faults in scan designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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It has been observed that random testing for delay faults can result in test sets of excessive length and high simulation costs. Consequently, we propose an efficient deterministic method of delay fault test generation. For most common circuits, our proposed technique has a time complexity which is polynomial in the size of the circuit, as opposed to existing deterministic methods which, for nearly all circuits, are exponential. We define a type of transition path, the fully transitional path, FTP, and demonstrate that it has several useful properties. An FTP can be created by applying a vector pair derived from a stuck-at test for a primary input, a technique introduced in [1]. We extend this method by using an alternate representation for switching functions, the binary decision diagram, to generate graphs representing stuck-at tests. The concept of free variables is defined as a tool for deriving several FTPs from one stuck-at test. Preliminary results are presented which indicate that our method provides a higher robust delay fault coverage than psuedorandom patterns at less than one-fifth the cost. Also, since vector pairs cannot be applied to combinational circuits using standard scan design, a simple scannable latch is introduced to facilitate this task.