Digital design: principles and practices (2nd ed.)
Digital design: principles and practices (2nd ed.)
VIPER: an efficient vigorously sensitizable path extractor
DAC '93 Proceedings of the 30th international Design Automation Conference
The kernel, the bargaining set and the reduced game
International Journal of Game Theory
A polynomial-time heuristic approach to approximate a solution to the false path problem
DAC '93 Proceedings of the 30th international Design Automation Conference
A method of delay fault test generation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Randomized algorithms in path sensitization for circuit optimization and delay fault tolerance
Randomized algorithms in path sensitization for circuit optimization and delay fault tolerance
Timing optimization by gate resizing and critical path identification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we consider the problems of identification of delay-fault-sensitive components in a pipelined combinational circuit, and of circuit modification to improve the circuit's tolerance of delay faults. The results assume purely combinational logic, and fixed gate delays calculated under floating delay mode.