On the general false path problem in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient algorithms for computing the longest viable path in a combinational network
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Static timing analysis of dynamically sensitizable paths
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
An efficient parallel critical path algorithm
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Incremental techniques for the identification of statically sensitizable critical paths
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Timing analysis with known false sub graphs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Event propagation conditions in circuit delay computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Path verification using Boolean satisfiability
Proceedings of the conference on Design, automation and test in Europe
Test generation for resistive opens in CMOS
Proceedings of the 12th ACM Great Lakes symposium on VLSI
False timing path identification using ATPG techniques and delay-based information
Proceedings of the 39th annual Design Automation Conference
Analyzing and improving delay defect tolerance in pipelined combinational circuits
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
On test coverage of path delay faults
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Effects of Multi-cycle Sensitization on Delay Tests
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A Novel Solution for Chip-Level Functional Timing Verification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Effective Path Selection for Delay Fault Testing of Sequential Circuits
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Critical Path Identification and Delay Tests of Dynamic Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Considering zero-arrival time and block-arrival time in hierarchical functional timing analysis
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Hi-index | 0.00 |