Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The Transduction Method-Design of Logic Networks Based on Permissible Functions
IEEE Transactions on Computers
On the general false path problem in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient algorithms for computing the longest viable path in a combinational network
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Static timing analysis of dynamically sensitizable paths
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient algorithms for extracting the K most critical paths in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
VIPER: an efficient vigorously sensitizable path extractor
DAC '93 Proceedings of the 30th international Design Automation Conference
The kernel, the bargaining set and the reduced game
International Journal of Game Theory
Event propagation conditions in circuit delay computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Device-circuit optimization for minimal energy and power consumption in CMOS random logic networks
DAC '97 Proceedings of the 34th annual Design Automation Conference
An Efficient Critical Path Tracing Algorithm for Designing HighPerformance Vlsi Systems
Journal of Electronic Testing: Theory and Applications
ETA: electrical-level timing analysis
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning
Proceedings of the 2003 international symposium on Physical design
Multi-objective circuit partitioning for cutsize and path-based delay minimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A Novel Solution for Chip-Level Functional Timing Verification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Proceedings of the 42nd annual Design Automation Conference
Three-dimensional place and route for FPGAs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A new LP based incremental timing driven placement for high performance designs
Proceedings of the 43rd annual Design Automation Conference
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