Timing driven placement using complete path delays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Incremental techniques for the identification of statically sensitizable critical paths
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Timing driven placement for large standard cell circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Unification of budgeting and placement
DAC '97 Proceedings of the 34th annual Design Automation Conference
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Timing influenced layout design
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A sensitivity based placer for standard cells
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Closing the gap between ASIC and custom: an ASIC perspective
Proceedings of the 37th Annual Design Automation Conference
Analytical minimization of half-perimeter wirelength
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Overcoming wireload model uncertainty during physical design
Proceedings of the 2001 international symposium on Physical design
Timing driven placement using physical net constraints
Proceedings of the 38th annual Design Automation Conference
Min-max placement for large-scale timing optimization
Proceedings of the 2002 international symposium on Physical design
Potential slack: an effective metric of combinational circuit performance
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A novel net weighting algorithm for timing-driven placement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Sensitivity guided net weighting for placement driven synthesis
Proceedings of the 2004 international symposium on Physical design
Incremental Placement for Timing Optimization
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Diffusion-based placement migration
Proceedings of the 42nd annual Design Automation Conference
How accurately can we model timing in a placement engine?
Proceedings of the 42nd annual Design Automation Conference
Computational geometry based placement migration
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm
Proceedings of the 2008 international symposium on Physical design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Path smoothing via discrete optimization
Proceedings of the 45th annual Design Automation Conference
Pyramids: an efficient computational geometry-based approach for timing-driven placement
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
ITOP: integrating timing optimization within placement
Proceedings of the 19th international symposium on Physical design
Timing-based placement considering uncertainty due to process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
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In this paper, we propose a new linear programming based timing driven placement framework for high performance designs. Our LP framework is mainly net-based, but it takes advantage of the path-based delay sensitivity with limited-stage slew propagation, thus it enjoys certain hybrid feature of net and path-based timing driven placement. Our LP formulation considers not only cells on the critical paths, but also cells that are logically adjacent to the critical paths (i.e., the criticality ad jacency network) in a unified manner. We further present a timing aware spreading method to preserve timing in legalization for high performance designs. Our algorithm has been tested on a set of 65nm industry circuits from a multi-GHz microprocessor, and shown to achieve much improved timing on hand-tuned circuits.