An iterative gate sizing approach with accurate delay evaluation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power vs. delay in gate sizing: conflicting objectives?
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power-delay optimizations in gate sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Timing driven placement using physical net constraints
Proceedings of the 38th annual Design Automation Conference
A novel net weighting algorithm for timing-driven placement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Gate sizing in MOS digital circuits with linear programming
EURO-DAC '90 Proceedings of the conference on European design automation
Incremental Placement for Timing Optimization
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Geometric programming for circuit optimization
Proceedings of the 2005 international symposium on Physical design
How accurately can we model timing in a placement engine?
Proceedings of the 42nd annual Design Automation Conference
A new LP based incremental timing driven placement for high performance designs
Proceedings of the 43rd annual Design Automation Conference
Simultaneous gate sizing and placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dominant critical gate identification for power and yield optimization in logic circuits
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Post-placement power optimization with multi-bit flip-flops
Proceedings of the International Conference on Computer-Aided Design
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Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power and timing are often conflicting objectives during optimization. In this paper, we propose a novel total power optimization flow under performance constraint. Instead of using placement, gate sizing, and multiple-Vt assignment techniques independently, we combine them together through the concept of slack distribution management to maximize the potential for power reduction. We propose to use the linear programming (LP) based placement and the geometric programming (GP) based gate sizing formulations to improve the slack distribution, which helps to maximize the total power reduction during the Vt-assignment stage. Our formulations include important practical design constraints, such as slew, noise and short circuit power, which were often ignored previously. We tested our algorithm on a set of industrial-strength manually optimized circuits from a multi-GHz 65nm microprocessor, and obtained very promising results. To our best knowledge, this is the first work that combines placement, gate sizing and Vt swapping systematically for total power (and in particular leakage) management.