Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Timing driven placement using physical net constraints
Proceedings of the 38th annual Design Automation Conference
Timing driven force directed placement with physical net constraints
Proceedings of the 2003 international symposium on Physical design
Timing-driven placement using design hierarchy guided constraint generation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Multi-objective circuit partitioning for cutsize and path-based delay minimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
How accurately can we model timing in a placement engine?
Proceedings of the 42nd annual Design Automation Conference
Timing-driven placement based on monotone cell ordering constraints
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
TAPHS: thermal-aware unified physical-level and high-level synthesis
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Adaptive chip-package thermal analysis for synthesis and design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A new LP based incremental timing driven placement for high performance designs
Proceedings of the 43rd annual Design Automation Conference
A network-flow approach to timing-driven incremental placement for ASICs
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Path smoothing via discrete optimization
Proceedings of the 45th annual Design Automation Conference
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Pyramids: an efficient computational geometry-based approach for timing-driven placement
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
ITOP: integrating timing optimization within placement
Proceedings of the 19th international symposium on Physical design
Timing yield optimization via discrete gate sizing using globally-informed delay PDFs
Proceedings of the International Conference on Computer-Aided Design
WRIP: logic restructuring techniques for wirelength-driven incremental placement
Proceedings of the great lakes symposium on VLSI
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An incremental timing driven placement algorithm is presented.We introduce a fast path-based analytical approach for timingimprovement. Our method achieves timing optimization byreducing the enclosing bounding boxes of selected nets oncritical paths. Furthermore, this technique tries to minimizemodifications to the initial placement while improving the delayof the circuit incrementally. Two contributions of this work are1) efficient conversion of a path-based timing minimizationproblem to a geometric net-constraint problem and 2) minimalmodification of a placement to improve timing. Our techniquecan take an initial placement from any algorithm and improvetiming iteratively. The experiments show that the proposedapproach is very efficient.