The scaling network simplex algorithm
Operations Research - Supplement
Incremental Placement for Timing Optimization
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Robust gate sizing by geometric programming
Proceedings of the 42nd annual Design Automation Conference
Circuit optimization using statistical static timing analysis
Proceedings of the 42nd annual Design Automation Conference
Statistical gate sizing for timing yield optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Variability driven gate sizing for binning yield optimization
Proceedings of the 43rd annual Design Automation Conference
A network-flow approach to timing-driven incremental placement for ASICs
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Gate sizing for cell library-based designs
Proceedings of the 44th annual Design Automation Conference
Statistical leakage power minimization using fast equi-slack shell based optimization
Proceedings of the 44th annual Design Automation Conference
Robust gate sizing via mean excess delay minimization
Proceedings of the 2008 international symposium on Physical design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Transistor sizing of custom high-performance digital circuits with parametric yield considerations
Proceedings of the 47th Design Automation Conference
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
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We develop two novel globally-informed gate-sizing algorithms for tackling the problems of statistical circuit timing optimization under a timing yield constraint, and timing yield optimization under a timing (i.e., delay) constraint. Unlike previous works, our techniques are global in the sense that they use objective functions that take into account either the entire circuit's variabilities and available gate sizes or those of the statistically timing-critical part of the circuit. The actual optimization, using the aforementioned objective functions, was performed using a recently introduced efficient discrete optimization technique called discretized network flow (DNF). We compared our algorithms to a state-of-the-art sensitivity based method. Experimental results show an absolute yield improvement of up to 43% and an average of 37% for the best of our two techniques over that of a non-statistical timing optimized circuit (optimized using a recent state-of-the-art method) based on the worst-case delay estimate for each gate. Our technique also gives a 19% better relative yield improvement over the sensitivity based method.