A cutting plane algorithm for convex programming that uses analytic centers
Mathematical Programming: Series A and B
Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
Convex Optimization
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
A New Statistical Optimization Algorithm for Gate Sizing
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
A New Method for Design of Robust Digital Circuits
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Proceedings of the 42nd annual Design Automation Conference
Correlation-aware statistical timing analysis with non-gaussian delay distributions
Proceedings of the 42nd annual Design Automation Conference
Robust gate sizing by geometric programming
Proceedings of the 42nd annual Design Automation Conference
Statistical gate sizing for timing yield optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty
Proceedings of the 43rd annual Design Automation Conference
Variability driven gate sizing for binning yield optimization
Proceedings of the 43rd annual Design Automation Conference
Digital Circuit Optimization via Geometric Programming
Operations Research
A Design Model for Random Process Variability
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variation-aware multimetric optimization during gate sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Evaluating statistical power optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing yield optimization via discrete gate sizing using globally-informed delay PDFs
Proceedings of the International Conference on Computer-Aided Design
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We introduce mean excess delay as a statistical measure of circuit delay in the presence of parameter variations. The β-mean excess delay is defined as the expected delay of the circuits that exceed the β-quantile of the delay, so it is always an upper bound on the β-quantile. However, in contrast to the β-quantile, it preserves the convexity properties of the underlying delay distribution. We apply the β-mean excess delay to the circuit sizing problem, and use it to minimize the delay quantile over the gate sizes. We use the Analytic Centering Cutting Plane Method to perform the minimization and apply this sizing to the ISCAS '85 benchmarks. Depending on the structure of the circuit, it can make significant improvements on the 95% quantile