A New Method for Design of Robust Digital Circuits

Authors:
Dinesh Patil;Sunghee Yun;Seung-Jean Kim;Alvin Cheung;Mark Horowitz;Stephen Boyd
Affiliations:
Stanford University, Stanford, CA;Stanford University, Stanford, CA;Stanford University, Stanford, CA;Stanford University, Stanford, CA;Stanford University, Stanford, CA;Stanford University, Stanford, CA
Venue:
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Year:
2005

Citing 10
Cited 16

Gradient-based optimization of custom circuits using a static-timing formulation

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A performance optimization method by gate sizing using statistical static timing analysis

ISPD '00 Proceedings of the 2000 international symposium on Physical design
Gate sizing using a statistical delay model

DATE '00 Proceedings of the conference on Design, automation and test in Europe
Uncertainty-aware circuit optimization

Proceedings of the 39th annual Design Automation Conference
Timing Yield Estimation from Static Timing Analysis

ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
A Family of Adders

ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
Convex Optimization

Convex Optimization
First-order incremental block-based statistical timing analysis

Proceedings of the 41st annual Design Automation Conference
Fast statistical timing analysis handling arbitrary delay correlations

Proceedings of the 41st annual Design Automation Conference
A methodology to improve timing yield in the presence of process variations

Proceedings of the 41st annual Design Automation Conference

Geometric programming for circuit optimization

Proceedings of the 2005 international symposium on Physical design
Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Application of fast SOCP based statistical sizing in the microprocessor design flow

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Mitigating the Impact of Process Variations on Processor Register Files and Execution Units

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Statistical circuit optimization considering device andinterconnect process variations

Proceedings of the 2007 international workshop on System level interconnect prediction
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Guaranteeing performance yield in high-level synthesis

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Digital Circuit Optimization via Geometric Programming

Operations Research
Robust gate sizing via mean excess delay minimization

Proceedings of the 2008 international symposium on Physical design
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in UDVS application

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
On the futility of statistical power optimization

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Timing-based placement considering uncertainty due to process variations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Evaluating statistical power optimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Theory and Applications of Robust Optimization

SIAM Review
Energy-delay space analysis for clocked storage elements under process variations

PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation

Quantified Score

Hi-index	0.00

Visualization

Abstract

As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations.Traditional circuit optimization methods assuming deterministic gate delays produce a flat "wall" of equally critical paths, resulting in variation-sensitive designs.This paper describes a new method for sizing of digital circuits, with uncertain gate delays, to minimize their performance variation leading to a higher parametric yield.The method is based on adding margins on each gate delay to account for variations and using a new "soft maximum" function to combine path delays at converging nodes.Using analytic models to predict the means and standard deviations of gate delays as posynomial functions of the device sizes, we create a simple, computationally efficient heuristic for uncertainty-aware sizing of digital circuits via Geometric programming.Monte-Carlo simulations on custom 32bit adders and ISCAS'85 benchmarks show that about 10% to 20% delay reduction over deterministic sizing methods can be achieved, without any additional cost in area.