Diminished-One Modulo 2^n +1 Adder Design
IEEE Transactions on Computers
Modulo 2n ± 1 Adder Design Using Select-Prefix Blocks
IEEE Transactions on Computers
A New Method for Design of Robust Digital Circuits
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Full-custom vs. standard-cell design flow: an adder case study
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Fast Modulo 2^{n} - (2^{n - 2} + 1) Addition: A New Class of Adder for RNS
IEEE Transactions on Computers
Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero
IEEE Transactions on Computers
Much ado about two (pearl): a pearl on parallel prefix computation
Proceedings of the 35th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Variable latency speculative addition: a new paradigm for arithmetic circuit design
Proceedings of the conference on Design, automation and test in Europe
Fast problem-size-independent parallel prefix circuits
Journal of Parallel and Distributed Computing
A 270ps 20mW 108-bit End-around Carry Adder for Multiply-Add Fused Floating Point Unit
Journal of Signal Processing Systems
Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A 32-bit carry lookahead adder using dual-path all-n logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Speculative carry generation with prefix adder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The algorithm and circuit design of a 400MHz 16-bit hybrid multiplier
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
A new optimized high-speed low-power data-driven dynamic (d3l) 32-bit kogge-stone adder
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Mathematical and Computer Modelling: An International Journal
Fast parallel prefix logic circuits for n2n round-robin arbitration
Microelectronics Journal
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Abstract: Binary carry-propagating addition can be efficiently expressed as a prefix computation. Several examples of adders based on such a formulation have been published, and efficient implementations are numerous. Chief among the known constructions are those of Kogge & Stone and Ladner & Fischer. In this work we show that these are end cases of a large family of addition structures, all of which share the attractive property of minimum logical depth. The intermediate structures allow trade-offs between the amount of internal wiring and the fanout of intermediate nodes, and can thus usually achieve a more attractive combination of speed and area/power cost than either of the known end-cases. Rules for the construction of such adders are given, as are examples of realistic 32b designs implemented in an industrial 0u25 CMOS process.