Residue number system arithmetic: modern applications in digital signal processing
Residue number system arithmetic: modern applications in digital signal processing
Computer arithmetic algorithms
Computer arithmetic algorithms
A proposal for a new block encryption standard
EUROCRYPT '90 Proceedings of the workshop on the theory and application of cryptographic techniques on Advances in cryptology
A Simplified Architecture for Modulo (2n + 1) Multiplication
IEEE Transactions on Computers
Journal of the ACM (JACM)
High-Speed Parallel-Prefix Modulo 2n - 1 Adders
IEEE Transactions on Computers - Special issue on computer arithmetic
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
A Reduced-Area Scheme for Carry-Select Adders
IEEE Transactions on Computers
Efficient VLSI Implementation of Modulo (2^n=B11) Addition and Multiplication
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
Modulo 2n ± 1 Adder Design Using Select-Prefix Blocks
IEEE Transactions on Computers
Fast Parallel-Prefix Modulo 2^n+1 Adders
IEEE Transactions on Computers
Efficient Diminished-1 Modulo 2^n+1 Multipliers
IEEE Transactions on Computers
Efficient modulo 2n+1 adder architectures
Integration, the VLSI Journal
Fast modulo 2n+1 multi-operand adders and residue generators
Integration, the VLSI Journal
DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
Improved area-efficient weighted modulo 2n+ 1 adder design with simple correction schemes
IEEE Transactions on Circuits and Systems II: Express Briefs
Efficient modulo 2n±1 squarers
Integration, the VLSI Journal
CSD-RNS-based Single Constant Multipliers
Journal of Signal Processing Systems
Area-time efficient multi-modulus adders and their applications
Microprocessors & Microsystems
Area-time efficient end-around inverted carry adders
Integration, the VLSI Journal
On the design of modulo 2n+1 dot product and generalized multiply-add units
Computers and Electrical Engineering
Efficient modulo 2n+1 multiply and multiply-add units based on modified Booth encoding
Integration, the VLSI Journal
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This paper presents two new design methodologies for modulo 2^n + 1 addition in the diminished-one number system. The first design methodology leads to carry look-ahead, whereas the second to parallel-prefix adder implementations. VLSI realizations of the proposed circuits in a standard-cell technology are utilized for quantitative comparisons against the existing solutions. Our results indicate that the proposed carry look-ahead adders are area and time efficient for small values of n, while for the rest values of n the proposed parallel-prefix adders are considerably faster than any other already known in the open literature.