Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
High-Speed Parallel-Prefix Modulo 2n - 1 Adders
IEEE Transactions on Computers - Special issue on computer arithmetic
Specialized hardware for real-time navigation
Real-Time Imaging
Computer Arithmetic Algorithms
Computer Arithmetic Algorithms
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Residue Number Systems: Algorithms and Architectures
Residue Number Systems: Algorithms and Architectures
An RNS Architecture for Quasi-Chaotic Oscillators
Journal of VLSI Signal Processing Systems
Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic
Journal of VLSI Signal Processing Systems
A Reduced-Area Scheme for Carry-Select Adders
IEEE Transactions on Computers
Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders
IEEE Transactions on Computers
Diminished-One Modulo 2^n +1 Adder Design
IEEE Transactions on Computers
Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies
Journal of VLSI Signal Processing Systems
Low-Power Constant-Coefficient Multiplier Generator
Journal of VLSI Signal Processing Systems
RDSP: A RISC DSP based on Residue Number System
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Some Optimizations of Hardware Multiplication by Constant Matrices
IEEE Transactions on Computers
A Low-Power FIR Filter Using Combined Residue and Radix-2 Signed-Digit Representation
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
Multiplierless multiple constant multiplication
ACM Transactions on Algorithms (TALG)
Multiplication by a Constant is Sublinear
ARITH '07 Proceedings of the 18th IEEE Symposium on Computer Arithmetic
Forward and Reverse Converters and Moduli Set Selection in Signed-Digit Residue Number Systems
Journal of Signal Processing Systems
Residue Number Systems: Theory and Implementation
Residue Number Systems: Theory and Implementation
A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations
IEEE Transactions on Computers
Time-efficient single constant multiplication based on overlapping digit patterns
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Circuits and Systems Part I: Regular Papers
How to Teach Residue Number System to Computer Scientists and Engineers
IEEE Transactions on Education
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Architectures for designing single constant multipliers in Residue Number System (RNS) for moduli of the 2 n 驴1, 2 n and 2 n 驴+驴1 forms are introduced with the constant operand being recoded in Signed-Digit representation. Two methodologies are proposed. In the first one a straightforward implementation of the shift-and-add algorithm is adopted, while in the second one a graph-based approach is used. Both methodologies result in circuits that are shown to be efficient in terms of area and delay.