High-Speed Parallel-Prefix Modulo 2n - 1 Adders

Authors:
Lampros Kalampoukas;Dimitris Nikolos;Costas Efstathiou;Haridimos T. Vergos;John Kalamatianos
Affiliations:
Xebeo Communications, Inc., South Plainfield, NJ;Univ. of Patras, Patras, Greece;TEI of Athens, Athens, Greece;Univ. of Patras, Patras, Greece;Northeastern Univ., Boston, MA
Venue:
IEEE Transactions on Computers - Special issue on computer arithmetic
Year:
2000

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Abstract

A novel parallel-prefix architecture for high speed modulo 2n-1 adders is presented. The proposed architecture is based on the idea of recirculating the generate and propagate signals, instead of the traditional end-around carry approach. Static CMOS implementations verify that the proposed architecture compares favorably with the already known parallel-prefix or carry look-ahead structures.