A Way to Build Efficient Carry-Skip Adders
IEEE Transactions on Computers
On the Complexity of Table Lookup for Iterative Division
IEEE Transactions on Computers
A Fast 1-D Serial-Parallel Systolic Multiplier
IEEE Transactions on Computers
Integer Division in Linear Time with Bounded Fan-In
IEEE Transactions on Computers
IEEE Transactions on Computers
A hardwired generalized algorithm for generating the logarithm base-k by iteration
IEEE Transactions on Computers
ACM '87 Proceedings of the 1987 Fall Joint Computer Conference on Exploring technology: today and tomorrow
A General Proof for Overlapped Multiple-Bit Scanning Multiplications
IEEE Transactions on Computers
Micro-optimization of floating-point operations
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Multiplier/Shifter Design Tradeoffs in a 32-bit Microprocessor
IEEE Transactions on Computers
Representational and Denotational Semantics of Digital Systems
IEEE Transactions on Computers
Parallel algorithm and VLSI architecture for a robot's inverse kinematics
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
The Design of a Testable Parallel Multiplier
IEEE Transactions on Computers
A Systematic Method for Division with High Average Bit Skipping
IEEE Transactions on Computers
The Testability of Generalized Counters Under Multiple Faulty Cells
IEEE Transactions on Computers
Radix-16 Signed-Digit Division
IEEE Transactions on Computers
The Set Theory of Arithmetic Decomposition
IEEE Transactions on Computers
An overview of supertoroidal networks
SPAA '91 Proceedings of the third annual ACM symposium on Parallel algorithms and architectures
A fast modular-multiplication algorithm based on a higher radix
CRYPTO '89 Proceedings on Advances in cryptology
A transistor reordering technique for gate matrix layout
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Test Generation for Iterative Logic Arrays Based on an N-Cube of Cell States Model
IEEE Transactions on Computers
GRIP: graphics reduced instruction processor
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Hard-Wired Multipliers with Encoded Partial Products
IEEE Transactions on Computers
Higher Radix Square Root with Prescaling
IEEE Transactions on Computers - Special issue on computer arithmetic
Low Latency Time CORDIC Algorithms
IEEE Transactions on Computers - Special issue on computer arithmetic
Fast Addition of Large Integers
IEEE Transactions on Computers
Bit-Parallel Arithmetic in a Massively-Parallel Associative Processor
IEEE Transactions on Computers
Decomposition of Complex Multipliers Using Polynomial Encoding
IEEE Transactions on Computers
Single-Precision Multiplier with Reduced Circuit Complexity for Signal Processing Applications
IEEE Transactions on Computers
Evaluation of A+B=K Conditions Without Carry Propagation
IEEE Transactions on Computers
Constant Time Inner Product and Matrix Computations on Permutation Network Processors
IEEE Transactions on Computers
Thoughts on parallelism and concurrency in compiling curricula
ACM Computing Surveys (CSUR)
A recursive algorithm for binary multiplication and its implementation
ACM Transactions on Computer Systems (TOCS)
Power analysis and low-power scheduling techniques for embedded DSP software
ISSS '95 Proceedings of the 8th international symposium on System synthesis
IEEE Transactions on Parallel and Distributed Systems
Carry-Save Multiplication Schemes Without Final Addition
IEEE Transactions on Computers
Hardware Starting Approximation Method and Its Application to the Square Root Operation
IEEE Transactions on Computers
A Novel Implementation of CORDIC Algorithm Using Backward Angle Recoding (BAR)
IEEE Transactions on Computers
A Fast Binary Adder with Conditional Carry Generation
IEEE Transactions on Computers
Novel Radix Finite Field Multiplier for GF(2^m)
Journal of VLSI Signal Processing Systems
A fast method for finding an integer square root
FORTH '90 and '91 Proceedings of the second and third annual workshops on Forth
Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions
IEEE Transactions on Computers
CMOS floating-point unit for the S/390 parallel enterprise server G4
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Arithmetic optimization using carry-save-adders
DAC '98 Proceedings of the 35th annual Design Automation Conference
Optimal Circuits for Parallel Multipliers
IEEE Transactions on Computers
Journal of VLSI Signal Processing Systems - Special issue on systematic trade-off analysis in signal processing systems design
Efficient Totally Self-Checking Shifter Design
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Reduction of latency and resource usage in bit-level pipelined data paths for FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
A CAD framework for generating self-checking multipliers based on residue codes
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Performance-driven scheduling with bit-level chaining
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A Radix 2 Shared Division/Square Root Algorithm and its VLSI Architecture
Journal of VLSI Signal Processing Systems
A design by example regular structure generator
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
An Effective Built-In Self-Test Scheme for Parallel Multipliers
IEEE Transactions on Computers
CSC '87 Proceedings of the 15th annual conference on Computer Science
A systolic multiplier unit and its VLSI design
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
New Efficient Structure for a Modular Multiplier for RNS
IEEE Transactions on Computers
Multiplierless Realization of Linear DSP Transforms by Using Common Two-Term Expressions
Journal of VLSI Signal Processing Systems
Signed Digit Addition and Related Operations with Threshold Logic
IEEE Transactions on Computers
Optimal allocation of carry-save-adders in arithmetic optimization
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Cost reduction and evaluation of temporary faults detecting technique
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Self-Timed Carry-Lookahead Adders
IEEE Transactions on Computers - Special issue on computer arithmetic
High-Speed Parallel-Prefix Modulo 2n - 1 Adders
IEEE Transactions on Computers - Special issue on computer arithmetic
High-Speed Booth Encoded Parallel Multiplier Design
IEEE Transactions on Computers - Special issue on computer arithmetic
Optimal Left-to-Right Binary Signed-Digit Recoding
IEEE Transactions on Computers - Special issue on computer arithmetic
Journal of VLSI Signal Processing Systems - special issue on CORDIC
An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits
IEEE Transactions on Computers
Digital filter synthesis based on minimal signed digit representation
Proceedings of the 38th annual Design Automation Conference
Representational error in binary and decimal numbering systems
ACM-SE 20 Proceedings of the 20th annual Southeast regional conference
High-Speed and Reduced-Area Modular Adder Structures for RNS
IEEE Transactions on Computers
Layout-aware synthesis of arithmetic circuits
Proceedings of the 39th annual Design Automation Conference
Towards a general framework for FPGA based image processing using hardware skeletons
Parallel Computing - Parallel computing in image and video processing
Fault-Secure Parity Prediction Arithmetic Operators
IEEE Design & Test
Fault-Secure Parity Prediction Booth Multipliers
IEEE Design & Test
A 20 Bit Logarithmic Number System Processor
IEEE Transactions on Computers
Some Results on a SRT Type Division Scheme
IEEE Transactions on Computers
Berger Check Prediction for Array Multipliers and Array Dividers
IEEE Transactions on Computers
Parallel High-Radix Nonrestoring Division
IEEE Transactions on Computers
High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits
IEEE Transactions on Computers
Accurate Rounding Scheme for the Newton-Raphson Method Using Redundant Binary Representation
IEEE Transactions on Computers
Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders
IEEE Transactions on Computers
Over-Redundant Digit Sets and the Design of Digit-By-Digit Division Units
IEEE Transactions on Computers
Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands
IEEE Transactions on Computers
Very-High Radix Division with Prescaling and Selection by Rounding
IEEE Transactions on Computers
Comparison of Reconfiguration Schemes for the C2SC MIN Operating in the Broadcast Mode
IEEE Transactions on Computers
Choices of Operand Truncation in the SRT Division Algorithm
IEEE Transactions on Computers
Division Using a Logarithmic-Exponential Transform to Form a Short Reciprocal
IEEE Transactions on Computers
Diminished-One Modulo 2^n +1 Adder Design
IEEE Transactions on Computers
Evolutionary Graph Generation System and Its Application to Bit-Serial Arithmetic Circuit Synthesis
PPSN VII Proceedings of the 7th International Conference on Parallel Problem Solving from Nature
Multiple-Wordlength Resource Binding
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Efficient Systolic Array Mapping of FIR Filters Used in PAM-QAM Modulators
Journal of VLSI Signal Processing Systems
Low-Power Constant-Coefficient Multiplier Generator
Journal of VLSI Signal Processing Systems
An effective BIST design for PLA
ATS '95 Proceedings of the 4th Asian Test Symposium
ARAS: asynchronous RISC architecture simulator
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Asynchronous Microengines for Efficient High-level Control
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Fault-secure shifter design: results and implementations
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A technology independent MOS multiplier generator
DAC '84 Proceedings of the 21st Design Automation Conference
Online pipeline systems for recursive numeric computations
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
Automatic generation of microprocessor test programs
DAC '82 Proceedings of the 19th Design Automation Conference
Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A 16-bit x 16-bit 1.2 /spl mu/ CMOS multiplier with low latency vector merging
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A single chip, pipelined, cascadable, multichannel, signal processor
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Delay-Insensitive Carry-Lookahead Adders
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Shift Switching with Domino Logic: Asynchronous VLSI Comparator Schemes
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Fixed-Width Multiplier for DSP Application
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Multiplication-free subband coding of color images
DCC '95 Proceedings of the Conference on Data Compression
EUDOXUS: A WWW-based Generator of Reusable Arithmetic Cores
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
Variable radix-2 multibit coding for 400 Mpixel/s DCT/IDCT of HDTV video decoder
Integration, the VLSI Journal
Deterministic BIST for RNS Adders
IEEE Transactions on Computers
Residue number system to binary converter for the moduli set (2n-1, 2n - 1, 2n + 1)
Journal of Systems Architecture: the EUROMICRO Journal
An arithmetic residue to binary conversion technique
Integration, the VLSI Journal
Evolutionary Synthesis of Arithmetic Circuit Structures
Artificial Intelligence Review
Design of a cycle-efficient 64-b/32-b integer divisor using a table-sharing algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Minimal Weight Digit Set Conversions
IEEE Transactions on Computers
Parallel encrypted array multipliers
IBM Journal of Research and Development - Nanostructure technology
An integrated approach to timing-driven synthesis and placement of arithmetic circuits
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
An improved synthesis method for low power hardwired FIR filters
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
From application descriptions to hardware in seconds: a logic-based approach to bridging the gap
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Tight integration of timing-driven synthesis and placement of parallel multiplier circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variable precision arithmetic circuits for FPGA-based multimedia processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Extensible multiplier-accumulator blocks for FPGAs
WISICT '05 Proceedings of the 4th international symposium on Information and communication technologies
A New Minimal Average Weight Representation for Left-to-Right Point Multiplication Methods
IEEE Transactions on Computers
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
The development of high performance FFT IP cores through hybrid low power algorithmic methodology
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A core generator for arithmetic cores and testing structures with a network interface
Journal of Systems Architecture: the EUROMICRO Journal
Evolutionary synthesis of arithmetic circuit structures
Artificial intelligence in logic design
Fault detection in switched current circuits using built-in transient current sensors
Journal of Electronic Testing: Theory and Applications
A Simple High-Speed Multiplier Design
IEEE Transactions on Computers
A new array architecture for signed multiplication using Gray encoded radix-2m operands
Integration, the VLSI Journal
Synthesis and Optimization of Programs by Means of P-Functions
IEEE Transactions on Computers
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
Limitations on Carry Lookahead Networks
IEEE Transactions on Computers
A Computer Algorithm for Calculating the Product AB Modulo M
IEEE Transactions on Computers
The Design of Easily Testable VLSI Array Multipliers
IEEE Transactions on Computers
A GaAs-Based Microprocessor Architecture for Real-Time Applications
IEEE Transactions on Computers
A Two's Complement Array Multiplier Using True Values of the Operands
IEEE Transactions on Computers
Computer Representation of Real Numbers
IEEE Transactions on Computers - Lecture notes in computer science Vol. 174
Partitioned Matrix Algorithms for VLSI Arithmetic Systems
IEEE Transactions on Computers
IP-checksum incremental update method proposal for efficient use of energy in wireless environments
EATIS '07 Proceedings of the 2007 Euro American conference on Telematics and information systems
A pipelined divider with a small lookup table
IMCAS'07 Proceedings of the 6th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems
Testing digital low-pass filters using oscillation-based test
Microprocessors & Microsystems
Comparison of redundant architectures for two-step ADCs
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Improving constant-coefficient multiplier verification by partial product identification
Proceedings of the conference on Design, automation and test in Europe
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
ICA3PP '09 Proceedings of the 9th International Conference on Algorithms and Architectures for Parallel Processing
Computers and Electrical Engineering
The S/390 G5 floating-point unit
IBM Journal of Research and Development
Fast modulo 2n+1 multi-operand adders and residue generators
Integration, the VLSI Journal
Area-efficient nonrestoring radix-2k division
Digital Signal Processing
An area-time efficient NMOS adder
Integration, the VLSI Journal
Resource requirements for the application of addition chains in modulo exponentiation
EUROCRYPT'92 Proceedings of the 11th annual international conference on Theory and application of cryptographic techniques
A robust channel estimator for high-mobility STBC-OFDM systems
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Monobit digital receivers: design, performance, and application to impulse radio
IEEE Transactions on Communications
A novel implementation of radix-4 floating-point division/square-root using comparison multiples
Computers and Electrical Engineering
CORDIC architectures: a survey
VLSI Design
A FPGA version of a non-linear adaptive filter
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination
Journal of Signal Processing Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bit-Sequential Arithmetic for Parallel Processors
IEEE Transactions on Computers
Proposed low power, high speed adder-based 65-nm Square root circuit
Microelectronics Journal
ICASSP'93 Proceedings of the 1993 IEEE international conference on Acoustics, speech, and signal processing: plenary, special, audio, underwater acoustics, VLSI, neural networks - Volume I
ICASSP'93 Proceedings of the 1993 IEEE international conference on Acoustics, speech, and signal processing: plenary, special, audio, underwater acoustics, VLSI, neural networks - Volume I
Power-delay product minimization in high-performance 64-bit carry-select adders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Modified Sliding-Block Distributed Arithmetic with Offset Binary Coding for Adaptive Filters
Journal of Signal Processing Systems
A logarithmic-depth quantum carry-lookahead adder
Quantum Information & Computation
Fast and energy-efficient constant-coefficient FIR filters using residue number system
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
A loopless gray code for minimal signed-binary representations
ESA'05 Proceedings of the 13th annual European conference on Algorithms
A logarithmic time method for two's complementation
ICCS'05 Proceedings of the 5th international conference on Computational Science - Volume Part I
CSD-RNS-based Single Constant Multipliers
Journal of Signal Processing Systems
On the design of modulo 2n-1 cubing units
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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