Computer number systems and arithmetic
Computer number systems and arithmetic
A General Proof for Overlapped Multiple-Bit Scanning Multiplications
IEEE Transactions on Computers
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Digital Computer Arithmetic
Introduction to Arithmetic for Digital Systems Designers
Introduction to Arithmetic for Digital Systems Designers
Parallel encrypted array multipliers
IBM Journal of Research and Development - Nanostructure technology
Strength reduction of multiplications by integer constants
ACM SIGPLAN Notices
Carry-Save Multiplication Schemes Without Final Addition
IEEE Transactions on Computers
Hardware Starting Approximation Method and Its Application to the Square Root Operation
IEEE Transactions on Computers
CMOS floating-point unit for the S/390 parallel enterprise server G4
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
DAC '98 Proceedings of the 35th annual Design Automation Conference
Comparison of Single- and Dual-Pass Multiply-Add Fused Floating-Point Units
IEEE Transactions on Computers
A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells
Journal of VLSI Signal Processing Systems
Correction to "Hard-Wired Multipliers with Encoded Partial Products"
IEEE Transactions on Computers
IEEE Transactions on Computers
Parallel High-Radix Nonrestoring Division
IEEE Transactions on Computers
Architecture and Implementation of a Vector/SIMD Multiply-Accumulate Unit
IEEE Transactions on Computers
The S/390 G5 floating-point unit
IBM Journal of Research and Development
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A multibit overlapped scanning multiplication algorithm for sign-magnitude and two's complement hard-wired multipliers is presented. The theorems necessary to construct the multiplication matrix for sign-magnitude representations are emphasized. Consequently, the algorithm for sign-magnitude multiplication and its variation to include two's complement numbers are presented. The proposed algorithm is compared to previous algorithms that generate a sign extended partial product matrix, with an implementation and with a study of the number of elements in the partial product matrix. The proposed algorithm is shown to yield significant savings over well known algorithms for the generation and the reduction of the partial product matrix of a multiplier designed with multibit overlapped scanning.