A General Proof for Overlapped Multiple-Bit Scanning Multiplications
IEEE Transactions on Computers
Hard-Wired Multipliers with Encoded Partial Products
IEEE Transactions on Computers
A single-chip IBM System/390 floating-point processor in CMOS
IBM Journal of Research and Development
CMOS floating-point unit for the S/390 parallel enterprise server G4
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Introduction to Arithmetic for Digital Systems Designers
Introduction to Arithmetic for Digital Systems Designers
Rounding for Quadratically Converging Algorithms for Division and Square Root
ASILOMAR '95 Proceedings of the 29th Asilomar Conference on Signals, Systems and Computers (2-Volume Set)
A Radix-8 CMOS S/390 Multiplier
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
The S/390 G5 Floating Point Unit Supporting Hex and Binary Architectures
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
Deep Submicron Design Techniques for the 500MHz IBM S/390 G5 Custom Microprocessor
ICCD '98 Proceedings of the International Conference on Computer Design
On Optimal Ierative Schemes for High-Speed Division
IEEE Transactions on Computers
On Division by Functional Iteration
IEEE Transactions on Computers
Some Properties of Iterative Square-Rooting Methods Using High-Speed Multiplication
IEEE Transactions on Computers
Custom S/390 G5 and G6 microprocessors
IBM Journal of Research and Development
IBM Journal of Research and Development
The IBM eServer z990 floating-point unit
IBM Journal of Research and Development
FPU Implementations with Denormalized Numbers
IEEE Transactions on Computers
ACM Transactions on Mathematical Software (TOMS)
Custom S/390 G5 and G6 microprocessors
IBM Journal of Research and Development
The microarchitecture of the IBM eServer z900 processor
IBM Journal of Research and Development
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The floating-point unit of the IBM S/390® G5 Parallel Enterprise Server represents a milestone in S/390 floating-point computation. The S/390 G5 contains the first floating-point unit (FPU) to support both the S/390 hexadecimal floating-point architecture and IEEE Standard 754 for binary floating-point arithmetic. The S/390 G5 FPU supports the new S/390 floating-point architecture, which contains six operand formats, including the IEEE 754 standard singleword, doubleword, and quadword formats, which are all supported in hardware. An internal hexadecimal-based dataflow is implemented to support both hexadecimal- and binary-based architectures. The S/390 G5 server is generally available at 500 MHz. The microprocessor chip is fabricated in IBM CMOS 6X technology, with a device size of 0.25 µm as drawn and 0.15 µm effective length. The design of the G5 FPU is based upon that of its predecessor, the G4. All of the custom dataflow macros from the G4 hexadecimal FPU were utilized with only minor modifications, and only a few additional macros for format conversion were required. This paper discusses the changes that were required to support the new S/390 binary floating-point architecture.