The microarchitecture of the IBM eServer z900 processor

  • Authors:

  • E. M. Schwarz;M. A. Check;C.-L. K. Shum;T. Koehler;S. B. Swaney;J. D. MacDougall;C. A. Krygowski

  • Affiliations:

  • IBM Server Group, Poughkeepsie, New York;IBM Server Group, Poughkeepsie, New York;IBM Server Group, Poughkeepsie, New York;IBM Server Group, Boeblingen Development Laboratory, Boeblingen, Germany;IBM Server Group, Poughkeepsie, New York;IBM Server Group, Poughkeepsie, New York;IBM Server Group, Poughkeepsie, New York

  • Venue:
  • IBM Journal of Research and Development
  • Year:
  • 2002

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Abstract

The recent IBM ESA/390 CMOS line of processors, from 1997 to 1999, consisted of the G4, G5, and G6 processors. The architecture they implemented lacked 64-bit addressability and had only a limited set of 64- bit arithmetic instructions. The processors also lacked data and instruction bandwidth, since they utilized a unified cache. The branch performance was good, but there were delays due to conflicts in searching and writing the branch target buffer. Also, the hardware data compression and decimal arithmetic performance, though good, was in demand by database and COBOL programmers. Most of the performance concerns regarding prior processors were due to area constraints. Recent technology advances have increased the circuit density by 50 percent over that of the G6 processor. This has allowed the design of several performance-critical areas to be revisited. The end result of these efforts is the IBM eServer z900 processor, which is the first high-end processor based on the new 64-bit z/Architecture™.